AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 259
![FPGA - Field Programmable Gate Array 250K System Gates](/photos/16/15/161503/landingpageactelfusion-2_sml.jpg)
AFS250-FGG256
Manufacturer Part Number
AFS250-FGG256
Description
FPGA - Field Programmable Gate Array 250K System Gates
Manufacturer
Actel
Datasheet
1.AFS600-PQG208.pdf
(330 pages)
Specifications of AFS250-FGG256
Processor Series
AFS250
Core
IP Core
Maximum Operating Frequency
1098.9 MHz
Number Of Programmable I/os
114
Data Ram Size
36864
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
250 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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The 1.76 W power is less than the required 3.00 W. The design therefore requires a heat sink, or the
airflow where the device is mounted should be increased. The design's total junction-to-air thermal
resistance requirement can be estimated by
Determining the heat sink's thermal performance proceeds as follows:
where
A heat sink with a thermal resistance of 5.01°C/W or better should be used. Thermal resistance of heat
sinks is a function of airflow. The heat sink performance can be significantly improved with increased
airflow.
Carefully estimating thermal resistance is important in the long-term reliability of an Actel FPGA. Design
engineers should always correlate the power consumption of the device with the maximum allowable
power dissipation of the package selected for that device.
Note: The junction-to-air and junction-to-board thermal resistances are based on JEDEC standard
(JESD-51) and assumptions made in building the model. It may not be realized in actual application and
therefore should be used with a degree of caution. Junction-to-case thermal resistance assumes that all
power is dissipated through the case.
Temperature and Voltage Derating Factors
Table 3-7 • Temperature and Voltage Derating Factors for Timing Delays
θ
θ
Array Voltage
VCC (V)
1.425
1.500
1.575
JA
SA
=
=
=
0.37°C/W
Thermal resistance of the interface material between
the case and the heat sink, usually provided by the
thermal interface manufacturer
Thermal resistance of the heat sink in °C/W
(normalized to T
–40°C
0.83
0.80
0.88
θ
SA
θ
ja(total)
=
J
13.33°C/W 8.28°C/W
= 70°C, Worst-Case VCC = 1.425 V)
=
0.93
0.88
0.85
0°C
θ
θ
T
------------------ -
JA(TOTAL)
SA
J
–
P
=
T
–
A
EQ
R e v i s i o n 1
θ
JA(TOTAL)
=
Junction Temperature (°C)
7:
100°C 70°C
----------------------------------- -
=
25°C
0.95
0.90
0.87
θ
3.00 W
JC
–
+
–
–
0.37°C/W
θ
θ
CS
JC
–
+
θ
θ
=
CS
SA
70°C
Actel Fusion Family of Mixed Signal FPGAs
1.00
0.95
0.91
10.00°C/W
=
5.01°C/W
85°C
1.02
0.96
0.93
100°C
1.05
0.99
0.96
EQ 7
EQ 8
EQ 9
3 -9
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