AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 51

• Manufacturer Part Number: AFS250-FGG256
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of AFS250-FGG256

• Processor Series: AFS250
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 114
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Real-Time Counter (part of AB macro)
The RTC is a 40-bit loadable counter and used as the primary timekeeping element
clock source, RTCCLK, must come from the CLKOUT signal of the crystal oscillator. The RTC can be
configured to reset itself when a count value reaches the match value set in the Match Register.
The RTC is part of the Analog Block (AB) macro. The RTC is configured by the analog configuration
MUX (ACM). Each address contains one byte of data. The circuitry in the RTC is powered by V
the RTC can be used in standby mode when the 1.5 V supply is not present.
Figure 2-29 • RTC Block Diagram
Table 2-14 • RTC Signal Description
The 40-bit counter can be preloaded with an initial value as a starting point by the Counter Register. The
count from the 40-bit counter can be read through the same set of address space. The count comes from
a Read-Hold Register to avoid data changing during read.
When the counter value equals the Match Register value, all Match Bits Register values will be
0xFFFFFFFFFF. The RTCMATCH and RTCPSMMATCH signals will assert. The 40-bit counter can be
configured to automatically reset to 0x0000000000 when the counter value equals the Match Register
value. The automatic reset does not apply if the Match Register value is 0x0000000000.
The RTCCLK has a prescaler to divide the clock by 128 before it is used for the 40-bit counter. Below is
an example of how to calculate the OFF time.
Signal Name
RTCCLK
RTCXTLMODE[1:0]
RTCXTLSEL
RTCMATCH
RTCPSMMATCH
Registers
ACM
Real-Time Counter
RTCCLK
1.5 V to
Shifter
Width Direction
3.3 V
Level
1
2
1
1
1
F
Crystal Prescaler
RTCCLK
Out
Out
Out
Out
In
Divide by 128
Must come from CLKOUT of XTLOSC.
Controlled by xt_mode in CTRL_STAT. Signal must connect to
the RTC_MODE signal in XTLOSC, as shown in
Controlled by xtal_en from CTRL_STAT register. Signal must
connect to RTC_MODE signal in XTLOSC in
Match signal for FPGA
0 – Counter value does not equal the Match Register value.
1 – Counter value equals the Match Register value.
Same signal as RTCMATCH. Signal must connect to
RTCPSMMATCH in VRPSM, as shown in
R e v i s i o n 1
Read-Hold Reg
Control Status
MatchBits Reg
40-Bit Counter
Counter Reg
Match Reg
Counter
Actel Fusion Family of Mixed Signal FPGAs
Function
xt_mode[1:0]
xtal_en
Figure
(Figure
RTCXTLMODE[1:0]
RTCPSMMATCH
RTCXTLSEL
RTCMATCH
Figure
Figure
2-27.
2-29). The
2-27.
CC33A
2-27.
2- 35
, so