AFS250-PQG208 Actel, AFS250-PQG208 Datasheet - Page 167

• Manufacturer Part Number: AFS250-PQG208
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of AFS250-PQG208

• Processor Series: AFS250
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 93
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Selectable Skew between Output Buffer Enable/Disable Time
The configurable skew block is used to delay the output buffer assertion (enable) without affecting
deassertion (disable) time.
Figure 2-105 • Block Diagram of Output Enable Path
Figure 2-106 • Timing Diagram (option1: bypasses skew circuit)
Figure 2-107 • Timing Diagram (option 2: enables skew circuit)
(from FPGA core)
ENABLE (OUT)
Output Enable
ENABLE (OUT)
ENABLE (IN)
ENABLE (IN)
ENABLE (IN)
Less than
0.1 ns
(typical)
1.2 ns
Skew Circuit
R e v i s i o n 1
Skew Select
MUX
Less than
0.1 ns
Less than
0.1 ns
Actel Fusion Family of Mixed Signal FPGAs
ENABLE (OUT)
I/O Output
Buffers
2- 151