LFXP2-5E-5FTN256C Lattice, LFXP2-5E-5FTN256C Datasheet - Page 14

• Manufacturer Part Number: LFXP2-5E-5FTN256C
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172I/O Inst- on DSP 1.2V -5 Spd
• Manufacturer: Lattice
• Series: LatticeXP2r

Specifications of LFXP2-5E-5FTN256C

• Number Of Macrocells: 5000
• Maximum Operating Frequency: 200 MHz
• Number Of Programmable I/os: 172
• Data Ram Size: 10 KB
• Supply Voltage (max): 1.14 V
• Supply Current: 17 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.26 V
• Package / Case: FTBGA-256
• No. Of Logic Blocks: 5000
• No. Of Macrocells: 2500
• Family Type: LatticeXP2
• No. Of Speed Grades: 5
• Total Ram Bits: 166Kbit
• No. Of I/o's: 172
• Clock Management: PLL
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Edge Clock Sources
Edge clock resources can be driven from a variety of sources at the same edge. Edge clock resources can be
driven from adjacent edge clock PIOs, primary clock PIOs, PLLs and clock dividers as shown in Figure 2-8.
Figure 2-8. Edge Clock Sources
Note: This diagram shows sources for the XP2-17 device. Smaller LatticeXP2 devices have two GPLLs.
From Routing
From Routing
Sources for left edge clocks
Input
Input
PLL
PLL
Clock
Clock
Input
Input
GPLL
GPLL
CLKOP
CLKOS
CLKOP
CLKOS
Routing
Routing
From
From
Eight Edge Clocks (ECLK)
Two Clocks per Edge
Clock Input
Clock Input
2-11
Clock Input
Clock Input
Routing
Routing
From
From
Sources for top
bottom edge
Sources for
edge clocks
clocks
LatticeXP2 Family Data Sheet
Sources for right edge clocks
CLKOP
CLKOS GPLL
CLKOP
CLKOS GPLL
Architecture
From Routing
From Routing
Clock
Clock
Input
Input
Input
Input
PLL
PLL