LFXP2-5E-5FTN256C Lattice, LFXP2-5E-5FTN256C Datasheet - Page 92

FPGA - Field Programmable Gate Array 5K LUTs 172I/O Inst- on DSP 1.2V -5 Spd

LFXP2-5E-5FTN256C

Manufacturer Part Number
LFXP2-5E-5FTN256C
Description
FPGA - Field Programmable Gate Array 5K LUTs 172I/O Inst- on DSP 1.2V -5 Spd
Manufacturer
Lattice
Series
LatticeXP2r
Datasheet

Specifications of LFXP2-5E-5FTN256C

Number Of Macrocells
5000
Maximum Operating Frequency
200 MHz
Number Of Programmable I/os
172
Data Ram Size
10 KB
Supply Voltage (max)
1.14 V
Supply Current
17 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.26 V
Package / Case
FTBGA-256
No. Of Logic Blocks
5000
No. Of Macrocells
2500
Family Type
LatticeXP2
No. Of Speed Grades
5
Total Ram Bits
166Kbit
No. Of I/o's
172
Clock Management
PLL
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LFXP2-5E-5FTN256C
Manufacturer:
LATTICE
Quantity:
1 001
Part Number:
LFXP2-5E-5FTN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LFXP2-5E-5FTN256C
Manufacturer:
LATTICE
Quantity:
20 000
Lattice Semiconductor
August 2008
June 2008
April 2008
April 2011
(cont.)
Date
Version
(cont.)
01.4
01.5
01.6
01.7
Characteristics (cont.)
Ordering Information
Pinout Information
Pinout Information
DC and Switching
DC and Switching
DC and Switching
DC and Switching
Characteristics
Characteristics
Characteristics
Architecture
Architecture
Section
Updated Flash Download Time (From On-Chip Flash to SRAM) Table
Updated Flash Program Time Table
Updated Flash Erase Time Table
Updated FlashBAK (from EBR to Flash) Table
Updated Hot Socketing Specifications Table footnotes
Updated Signal Descriptions Table
Removed Read-Before-Write sysMEM EBR mode.
Clarification of the operation of the secondary clock regions.
Removed Read-Before-Write sysMEM EBR mode.
Updated DDR Banks Bonding Out per I/O Bank section of Pin Informa-
tion Summary Table.
Data sheet status changed from preliminary to final.
Clarification of the operation of the secondary clock regions.
Removed “8W” specification from Hot Socketing Specifications table.
Removed "8W" footnote from DC Electrical Characteristics table.
Updated Register-to-Register Performance table.
Removed “8W” option from Part Number Description.
Removed XP2-17 “8W” OPNs.
Recommended Operating Conditions table, added footnote 5.
On-Chip Flash Memory Specifications table, added footnote 1.
BLVDS DC Conditions, corrected column title to be Z0 = 90 ohms.
sysCONFIG Port Timing Specifications table, added footnote 1 for 
t
DINIT
.
7-2
Change Summary
LatticeXP2 Family Data Sheet
Revision History

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