LFXP2-5E-5FTN256C Lattice, LFXP2-5E-5FTN256C Datasheet - Page 18

• Manufacturer Part Number: LFXP2-5E-5FTN256C
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172I/O Inst- on DSP 1.2V -5 Spd
• Manufacturer: Lattice
• Series: LatticeXP2r

Specifications of LFXP2-5E-5FTN256C

• Number Of Macrocells: 5000
• Maximum Operating Frequency: 200 MHz
• Number Of Programmable I/os: 172
• Data Ram Size: 10 KB
• Supply Voltage (max): 1.14 V
• Supply Current: 17 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.26 V
• Package / Case: FTBGA-256
• No. Of Logic Blocks: 5000
• No. Of Macrocells: 2500
• Family Type: LatticeXP2
• No. Of Speed Grades: 5
• Total Ram Bits: 166Kbit
• No. Of I/o's: 172
• Clock Management: PLL
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-14. Slice0 through Slice2 Control Selection
Edge Clock Routing
LatticeXP2 devices have eight high-speed edge clocks that are intended for use with the PIOs in the implementa-
tion of high-speed interfaces. Each device has two edge clocks per edge. Figure 2-15 shows the selection muxes
for these clocks.
Figure 2-15. Edge Clock Mux Connections
Secondary Clock
GPLL Output CLKOP
GPLL Output CLKOS
Clock Input Pad
GPLL Input Pad
GPLL Input Pad
Routing
Vcc
Input Pad
Input Pad
Routing
Routing
Routing
12
3
1
2-15
16:1
Top and Bottom
ECLK1/ ECLK2
Left and Right
Left and Right
(Both Muxes)
Edge Clocks
Edge Clocks
Edge Clocks
ECLK1
ECLK2
Slice Control
LatticeXP2 Family Data Sheet
Architecture