ML610Q428-NNNTBZ03A7 Rohm Semiconductor, ML610Q428-NNNTBZ03A7 Datasheet - Page 126
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ML610Q428-NNNTBZ03A7
Manufacturer Part Number
ML610Q428-NNNTBZ03A7
Description
MCU 8BIT 48K FLASH 128-TQFP
Manufacturer
Rohm Semiconductor
Datasheets
1.ML610Q482P-NNNTB03A7.pdf
(20 pages)
2.ML610Q428-NNNTBZ03A7.pdf
(32 pages)
3.ML610Q428-NNNTBZ03A7.pdf
(434 pages)
Specifications of ML610Q428-NNNTBZ03A7
Core Processor
nX-U8/100
Core Size
8-Bit
Speed
4.2MHz
Connectivity
I²C, SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 2x12b, 2x24b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ML610Q428-NNNTBZ03A7
Manufacturer:
ROHM
Quantity:
750
Company:
Part Number:
ML610Q428-NNNTBZ03A7
Manufacturer:
Rohm Semiconductor
Quantity:
10 000
- ML610Q482P-NNNTB03A7 PDF datasheet
- ML610Q428-NNNTBZ03A7 PDF datasheet #2
- ML610Q428-NNNTBZ03A7 PDF datasheet #3
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- Download datasheet (3Mb)
9.2.5
Address: 0F035H
Access: R/W
Access size: 8 bits
Initial value: 00H
TM1C is a special function register (SFR) that functions as an 8-bit binary counter.
When write operation to TM1C is performed, TM1C is set to “00H”. The data that is written is meaningless.
In 16-bit timer mode, if write operation is performed to either the low-order TM0C or high-order TM1C, both the low
order and the high order are set to “0000H”.
When reading TM1C in 16-bit timer mode, be sure to read TM0C first since the count value of TM1C is stored in the
TM1C latch when TM0C is read.
During timer operation, the contents of TM1C may not be read depending on the conditions of the timer clock and the
system clock.
Table 11-2 shows whether a TM1C read is enabled or disabled during timer operation for each condition of the timer
clock and system clock.
Initial value
TM1C
R/W
External clock
Timer clock
Timer 1 Counter Register (TM1C)
HTBCLK
HTBCLK
LSCLK
LSCLK
T1CK
T1C7
R/W
7
0
Table 9-2 TM1C Read Enable/Disable during Timer Operation
1/1~1/256LSCLK
1/1~1/256LSCLK
1/1~1/256LSCLK
System clock
T1C6
R/W
SYSCLK
0
6
HSCLK
HSCLK
HSCLK
T1C5
R/W
5
0
Read enabled
Read enabled. However, to prevent the reading of undefined
data during incremental counting, read consecutively TM1C twice
until the last data coincides the previous data
Read disabled
Read enabled
Read disabled
T1C4
R/W
4
0
9 – 6
T1C3
R/W
TM1C read enable/disable
3
0
ML610Q428/ML610Q429 User’s Manual
T1C2
R/W
2
0
T1C1
R/W
0
1
Chapter 9 Timers
T1C0
R/W
0
0
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