ML610Q428-NNNTBZ03A7 Rohm Semiconductor, ML610Q428-NNNTBZ03A7 Datasheet - Page 364
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ML610Q428-NNNTBZ03A7
Manufacturer Part Number
ML610Q428-NNNTBZ03A7
Description
MCU 8BIT 48K FLASH 128-TQFP
Manufacturer
Rohm Semiconductor
Datasheets
1.ML610Q482P-NNNTB03A7.pdf
(20 pages)
2.ML610Q428-NNNTBZ03A7.pdf
(32 pages)
3.ML610Q428-NNNTBZ03A7.pdf
(434 pages)
Specifications of ML610Q428-NNNTBZ03A7
Core Processor
nX-U8/100
Core Size
8-Bit
Speed
4.2MHz
Connectivity
I²C, SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 2x12b, 2x24b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ML610Q428-NNNTBZ03A7
Manufacturer:
ROHM
Quantity:
750
Company:
Part Number:
ML610Q428-NNNTBZ03A7
Manufacturer:
Rohm Semiconductor
Quantity:
10 000
- ML610Q482P-NNNTB03A7 PDF datasheet
- ML610Q428-NNNTBZ03A7 PDF datasheet #2
- ML610Q428-NNNTBZ03A7 PDF datasheet #3
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- Download datasheet (3Mb)
ML610Q428/ML610Q429 User’s Manual
Chapter 24 LCD Drivers
In display allocation register A (DSmCnA: m = 0 to 63, n = 0 to 8), set the lower 8 bits (00H to 0FEH) of the addresses
of the display registers (DSPR00 to DSPRFE) that are output to common n of segment n. In display allocation register B
(DSmCnB: m = 0 to 63, n = 0 to 8), set the bits of the display registers (DSPR00 to DSPRFE) that are output to common
n of segment m.
For instance, to display bit 6 of display register 23 to common 3 of segment 16, set as follows.
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
DS16C3A
0
0
1
0
0
0
1
1
DS16C3B
*
*
*
*
*
1
1
0
(0F416H)
(0F616H)
Address specification of display register
Bit specification of display register
"*" indicates an arbitrary value.
Note:
- Set display allocation data to display allocation registers A and B when the DASN bit of display control register 0
(DSPMOD1) is “0”. When the DASN bit is “1”, access from the CPU is invalid.
- Select type 3 for the display register segment map (Set DADM1 bit of DSPMOD1 register to “1”) when using the
programmable allocation function.
24 – 46
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