ML610Q428-NNNTBZ03A7 Rohm Semiconductor, ML610Q428-NNNTBZ03A7 Datasheet - Page 213

• Manufacturer Part Number: ML610Q428-NNNTBZ03A7
• Description: MCU 8BIT 48K FLASH 128-TQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q428-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.3 Description of Operation
14.3.1
I
14.3.1.1
14.3.1.2
14.3.1.3
14.3.1.4
14.3.1.5
is received in the I20ACR bit of the I
14.3.1.6
14.3.1.7 Stop Condition
Communication is started when communication mode is selected by using the I
bus 0 slave address register, and “1” is written to the I20ST bit of the I2C bus 0 control register (I2C0CON).
When “1” is written to the I20ST bit of the I
I20ST bit is “0”), communication is started and the start condition waveform is output to the SDA and SCL pins.
After execution of the start condition, the LSI shifts to slave address transmit mode.
When “1” is written to the I20RS and I20ST bits of the I
(the I20ST bit is “0”), the restart condition waveform is output to the SDA and SCL pins.
After execution of the restart condition, the LSI shifts to slave address transmit mode.
In slave address transmit mode, the values (slave address and data communication direction) of the I
address register (I2C0SA) are transmitted in MSB first, and finally, the acknowledgment signal is received in the
I20ACR bit of the I
At completion of acknowledgment reception, the LSI shifts to the I
state (control register setting wait state).
The value of I2C0SA output from the SDA pin is stored in I2C0RD.
In data transmit mode, the value of I2C0TD is transmitted in MSB first, and finally, the acknowledgment signal is
received in the I20ACR bit of the I
At completion of acknowledgment reception, the LSI shifts to the I
state (control register setting wait state).
The value of I2C0TD output from the SDA pin is stored in I2C0RD.
In data receive mode, the value input in the SDA pin is received synchronously with the rising edge of the serial clock
output to the SCL pin, and finally, the value of the I20ACT bit of the I2C bus 0 control register (I2C0CON) is output.
At completion of acknowledgment transmission, the LSI shifts to the I
state (control register setting wait state).
The data received is stored in I2C0RD after the acknowledgment signal is output. The acknowledgment signal output
When the LSI shifts to the control register setting wait state, an I
In the control register setting wait state, the transmit flag (I20ER) of the I
acknowledgment receive data (I20ACR) are confirmed and at data reception, the contents of I2C0RD are read in the
CPU and the next operation mode is selected.
When “1” is written to the I20ST bit in the control register setting wait state, the LSI shifts to the data transmit or
receive mode. When “1” is written to the I20SP bit, the LSI shifts to the stop condition. When “1” is written to the
I20RS bit, the operation shifts to the restart condition.
In the stop condition, the stop condition waveform is output to the SDA and SCL pins. After the stop condition
waveform is output, an I
2
C function is enabled by using the I20EN bit, a slave address and a data communication direction are set in the I
Communication Operating Mode
Start Condition
Restart Condition
Slave Address Transmit Mode
Data Transmit Mode
Data Receive Mode
Control Register Setting Wait State
2
C bus 0 status register (I2CSTAT).
2
C bus interface interrupt (I2C0INT) is generated.
2
C bus 0 status register (I2CSTAT).
2
C bus 0 status register (I2CSTAT).
2
C bus 0 control register ((I2C0CON) while communication is stopped (the
14 – 9
2
C bus 0 control register ((I2C0CON) during communication
2
C bus interface interrupt (I2C0INT) is generated.
2
2
C bus 0 control register (I2C0CON) setting wait
C bus 0 control register (I2C0CON) setting wait
2
C bus 0 control register (I2C0CON) setting wait
ML610Q428/ML610Q429 User’s Manual
2
C bus 0 status register (I2C0STAT) and
2
C bus 0 mode register (I2C0MOD), the
Chapter 14 I
2
C Bus Interface
2
C bus 0 slave
2
C