ML610Q432A-NNNTC03A7 Rohm Semiconductor, ML610Q432A-NNNTC03A7 Datasheet
ML610Q432A-NNNTC03A7
Specifications of ML610Q432A-NNNTC03A7
Available stocks
Related parts for ML610Q432A-NNNTC03A7
ML610Q432A-NNNTC03A7 Summary of contents
Page 1
ML610Q431/ML610Q432 User’s Manual FEUL610Q431-01 Issue Date: July 5, 2010 ...
Page 2
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application ...
Page 3
This manual describes the operation of the hardware of the 8-bit microcontroller ML610Q431/ML610Q432. The following manuals are also available. Read them as necessary. nX-U8/100 Core Instruction Manual Description on the basic architecture and the each instruction of the MACU8 Assembler ...
Page 4
Classification Notation ♦ Numeric value xxh, xxH xxb ♦ Unit word, W byte, B nibble, N maga-, M kilo-, K kilo-, k milli-, m micro-, µ nano-, n second, s (lower case) ♦ Terminology “H” level, “1” level “L” level, ...
Page 5
Chapter 1 1. Overview ........................................................................................................................................................ 1-1 1.1 Features....................................................................................................................................................... 1-1 1.2 Configuration of Functional Blocks............................................................................................................ 1-4 1.2.1 Block Diagram of ML610Q431.......................................................................................................... 1-4 1.2.2 Block Diagram of ML610Q432.......................................................................................................... 1-5 1.3 Pins ............................................................................................................................................................. 1-6 1.3.1 Pin Layout........................................................................................................................................... 1-6 1.3.1.1 Pin Layout of ML610Q431 ...
Page 6
Block Control Register 2 (BLKCON2) .............................................................................................. 4-7 4.2.7 Block Control Register 3 (BLKCON3) .............................................................................................. 4-8 4.2.8 Block Control Register 4 (BLKCON4) .............................................................................................. 4-9 4.3 Description of Operation........................................................................................................................... 4-11 4.3.1 Program Run Mode........................................................................................................................... 4-11 4.3.2 HALT Mode ..................................................................................................................................... 4-11 4.3.3 ...
Page 7
Crystal/Ceramic Oscillation Mode .................................................................................................. 6-9 6.3.2.3 Built-in PLL Oscillation Mode...................................................................................................... 6-10 6.3.2.4 External Clock Input Mode ........................................................................................................... 6-10 6.3.2.5 Operation of High-Speed Clock Generation Circuit...................................................................... 6-11 6.3.3 Switching of System Clock............................................................................................................... 6-13 6.4 Specifying port registers ........................................................................................................................... 6-15 6.4.1 ...
Page 8
List of Registers ........................................................................................................................................ 9-2 9.2.2 Capture Control Register (CAPCON)................................................................................................. 9-3 9.2.3 Capture Status Register (CAPSTAT) ................................................................................................. 9-4 9.2.4 Capture Data Register 0 (CAPR0) ...................................................................................................... 9-5 9.2.5 Capture Data Register 1 (CAPR1) ...................................................................................................... 9-6 9.3 Description of Operation............................................................................................................................. 9-7 ...
Page 9
Description of Operation........................................................................................................................... 12-8 12.4 Specifying port registers ......................................................................................................................... 12-10 12.4.1 Functioning P43 (PWM0) as the PWM output ............................................................................... 12-10 12.4.2 Functioning P34 (PWM0) as the PWM output ............................................................................... 12-11 Chapter 13 13. Watchdog Timer ........................................................................................................................................... 13-1 13.1 Overview................................................................................................................................................... ...
Page 10
Transmit Data Direction ................................................................................................................. 15-13 15.3.4 Transmit Operation ......................................................................................................................... 15-14 15.3.5 Receive Operation........................................................................................................................... 15-16 15.4 Specifying port registers ......................................................................................................................... 15-18 15.4.1 Functioning P43(TXD0) and P42(RXD0) as the UART ................................................................ 15-18 15.4.2 Functioning P43(TXD0) and P02(RXD0) as the UART ................................................................ ...
Page 11
Port 0 Data Register (P0D) ............................................................................................................... 18-3 18.2.3 Port 0 Control Registers 0, 1 (P0CON0, P0CON1) .......................................................................... 18-4 18.2.4 External Interrupt Control Registers 0, 1 (EXICON0, EXICON1)................................................... 18-5 18.2.5 External Interrupt Control Register 2 (EXICON2) ........................................................................... 18-6 18.3 Description ...
Page 12
Overview................................................................................................................................................... 22-1 22.1.1 Features............................................................................................................................................. 22-1 22.1.2 Configuration .................................................................................................................................... 22-1 22.1.3 List of Pins........................................................................................................................................ 22-2 22.2 Description of Registers............................................................................................................................ 22-3 22.2.1 List of Registers ................................................................................................................................ 22-3 22.2.2 Port 4 Data Register (P4D) ............................................................................................................... 22-4 22.2.3 Port 4 Direction Register (P4DIR).................................................................................................... ...
Page 13
Description of Registers............................................................................................................................ 25-3 25.2.1 List of Registers ................................................................................................................................ 25-3 25.2.2 RC-ADC Counter A Registers (RADCA0–2) .................................................................................. 25-4 25.2.3 RC-ADC Counter B Registers (RADCB0–2)................................................................................... 25-5 25.2.4 RC-ADC Mode Register (RADMOD) ............................................................................................. 25-6 25.2.5 RC-ADC Control Register (RADCON)............................................................................................ 25-7 25.3 ...
Page 14
Display Registers (DSPR00 to DSPRFE) ....................................................................................... 27-20 27.3 Description of Operation......................................................................................................................... 27-35 27.3.1 Operation of LCD Drivers and Bias Generation Circuit................................................................. 27-35 27.3.2 Segment Mapping When the Programmable Display Allocation Function is Not Used ................ 27-36 27.3.3 Segment Mapping ...
Page 15
Chapter 1 Overview ...
Page 16
Overview 1.1 Features This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as real-time clock, synchronous serial port, UART, I type A/D converter, 12-bit successive approximation type A/D converter, and LCD driver, are incorporated ...
Page 17
Capture − Time base capture × 2 channels (4096 Hz) • PWM − Resolution 16 bits × 1 channel • Real time clock − Year, month, day, day of the week, hour, minute, and second registers ...
Page 18
LCD driver − Dot matrix can be supported. ML610Q431: 1024 dots max. (64 seg × 16 com) ML610Q432: 1536 dots max. (64 seg × 24 com) − 1/1 to 1/24 duty − 1/3 or 1/4 bias (built-in bias generation ...
Page 19
Configuration of Functional Blocks 1.2.1 Block Diagram of ML610Q431 EPSW1∼3 PSW Timing Controller On-Chip ICE RESET_N RESET & TEST TEST XT0 XT1 OSC0* OSC OSC1* LSCLK* OUTCLK* V DDL Power V DDX IN0* CS0* RS0* ...
Page 20
Block Diagram of ML610Q432 EPSW1∼3 PSW Timing Controller On-Chip ICE RESET_N RESET & TEST TEST XT0 XT1 OSC0* OSC OSC1* LSCLK* OUTCLK* V DDL Power V DDX INT 1 IN0* CS0* RS0* RT0* RC-ADC CRT0* ...
Page 21
Pins 1.3.1 Pin Layout 1.3.1.1 Pin Layout of ML610Q431 LQFP Package 108pin 109pin SEG47 SEG48 11 SEG49 11 SEG50 11 SEG51 11 SEG52 11 SEG53 11 SEG54 11 SEG55 11 SEG56 12 ...
Page 22
Pin Layout of ML610Q432 LQFP Package 108pin 109pin SEG47 SEG48 11 SEG49 11 SEG50 11 SEG51 11 SEG52 11 SEG53 11 SEG54 11 SEG55 11 SEG56 12 SEG57 12 SEG58 12 SEG59 ...
Page 23
Pin Layout of ML610Q431 Chip SEG46 98 SEG47 99 VDD 100 VPP 101 SEG48 102 SEG49 103 SEG50 104 SEG51 105 SEG52 106 SEG53 107 SEG54 108 SEG55 109 SEG56 110 SEG57 111 SEG58 112 SEG59 113 SEG60 114 ...
Page 24
Pin Layout of ML610Q432 Chip SEG46 98 SEG47 99 VDD 100 VPP 101 SEG48 102 SEG49 103 SEG50 104 SEG51 105 SEG52 106 SEG53 107 SEG54 108 SEG55 109 SEG56 110 SEG57 111 SEG58 112 SEG59 113 SEG60 114 ...
Page 25
Pad Coordinates of ML610Q431 Chip PAD Pad X No. Name (μm) 1 P01 -1400 2 P00 -1300 3 NMI -1200 4 V -1100 SS 5 P20 -1000 6 P21 -900 7 P22 -800 8 P40 -700 9 P41 -600 ...
Page 26
Pad Coordinates of ML610Q432 Chip PAD Pad X No. Name (μm) 1 P01 -1400 2 P00 -1300 3 NMI -1200 4 V -1100 SS 5 P20 -1000 6 P21 -900 7 P22 -800 8 P40 -700 9 P41 -600 ...
Page 27
List of Pins PAD No. Primary function Q432 Q431 Pin name I/O Negative power ⎯ 4,26 4,26 Vss supply pin Positive power supply ⎯ 28,100 28,100 V DD pin Power supply pin for ⎯ internal logic ...
Page 28
PAD No. Primary function Q432 Q431 Pin name I/O Successive approximation type 133 133 AIN0 I ADC input Successive approximation type 134 134 AIN1 I ADC input Non-maskable 3 3 NMI I interrupt pin Input port, External P00/EXI interrupt 0, ...
Page 29
PAD No. Primary function Q432 Q431 Pin name I/O Input/output port ⎯ 32 PA0 I/O Input/output port ⎯ 33 PA1 I/O Input/output port ⎯ 34 PA2 I/O ⎯ Input/output port 35 PA3 I/O Input/output port ⎯ 36 PA4 I/O Input/output ...
Page 30
PAD No. Primary function Q432 Q431 Pin name I/O LCD segment pin 69 69 SEG17 O LCD segment pin 70 70 SEG18 O LCD segment pin 71 71 SEG19 O LCD segment pin 72 72 SEG20 O LCD segment pin ...
Page 31
Description of Pins Pin name I/O System Reset input pin. When this pin is set to a “L” level, system reset mode is RESET_N I set and the internal section is initialized. When this pin is set to a ...
Page 32
Pin name I/O UART UART data output pin. This pin is used as the secondary function of the TXD0 O P43 pin. UART data input pin. This pin is used as the secondary function of the RXD0 I P42 or ...
Page 33
Pin name I/O RC oscillation type A/D converter Channel 0 oscillation input pin. This pin is used as the secondary function IN0 I of the P30 pin. Channel 0 reference capacitor connection pin. This pin is used as the CS0 ...
Page 34
Pin name I/O Plus-side power supply pin (internally generated) for low-speed oscillation. V — DDX Capacitor Cx (see measuring circuit 1) is connected between this pin and Power supply pin for programming Flash ROM. A pull-up resistor ...
Page 35
Termination of Unused Pins Table 1-3 shows methods of terminating the unused pins. Pin REF AIN0, AIN1 C1, C2, C3, C4 ...
Page 36
CPU and Memory Space Chapter 2 ...
Page 37
CPU and Memory Space 2.1 Overview This LSI includes 8-bit CPU nX-U8/100 and the memory model is “SMALL model” . For details of the CPU nX-U8/100, see “nX-U8/100 Core Instruction Manual”. 2.2 Program Memory Space The program memory space ...
Page 38
Data Memory Space The data memory space of this LSI consists of the ROM window area, 2KByte RAM area and SFR area of Segment 0 and the ROM reference areas of the Segment 1 and Segment 8. The data ...
Page 39
Description of Registers 2.6.1 List of Registers Address Name 0F000H Data segment register ML610Q431/ML610Q432 User’s Manual Chapter 2 CPU and Memory Space Symbol (Byte) Symbol (Word) ⎯ DSR 2 – 3 R/W Size Initial value R/W 8 00H ...
Page 40
Data Segment Register (DSR) Address: 0F000H Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ DSR R/W R/W R/W Initial value 0 0 DSR is a special function register (SFR) to retain a data segment. ...
Page 41
Chapter 3 Reset Function ...
Page 42
Reset Function 3.1 Overview This LSI has the five reset functions shown below. If any of the five reset conditions is satisfied, this LSI enters system reset mode. • Reset by the RESET_N pin • Reset by power-on detection ...
Page 43
Description of Registers 3.2.1 List of Registers Address Name 0F001H Reset status register 3.2.2 Reset Status Register (RSTAT) Address: 0F001H Access: R/W Access size: 8 bits Initial value: Undefined 7 6 RSTAT ― ― R/W R/W R/W Initial value ...
Page 44
Description of Operation 3.3.1 Operation of System Reset Mode System reset has the highest priority among all the processings and any other processing being executed up to then is cancelled. The system reset mode is set by any of ...
Page 45
MCU Control Function Chapter 4 ...
Page 46
MCU Control Function 4.1 Overview The operating states of this LSI are classified into the following 4 modes including system reset mode: System reset mode Program run mode HALT mode STOP mode For system reset mode, see Chapter 3, ...
Page 47
Description of Registers 4.2.1 List of Registers Address Name Stop code acceptor 0F008H Standby control register 0F009H Block control register 0 0F028H 0F029H Block control register 1 0F02AH Block control register 2 Block control register 3 0F02BH Block control ...
Page 48
Stop Code Acceptor (STPACP) Address: 0F008H Access: W Access size: 8 bits Initial value: ⎯ (Undefined STPACP ― ― Initial value ― ― STPACP is a write-only special function register (SFR) that is used ...
Page 49
Standby Control Register (SBYCON) Address: 0F009H Access: W Access size: 8 bits Initial value: 00H 7 6 SBYCON ― ― Initial value 0 0 SBYCON is a special function register (SFR) to control operating mode of ...
Page 50
Block Control Register 0(BLKCON0) Address: 0F028H Access: R/W Access size: 8 bits Initial value: 00H 7 6 BLKCON0 ― ― R/W R/W R/W Initial value 0 0 BLKCON0 is a special function register (SFR) to make even more reducing ...
Page 51
Block Control Register 1(BLKCON1) Address: 0F029H Access: R/W Access size: 8 bits Initial value: 00H 7 6 BLKCON1 ― DCAPR R/W R/W R/W Initial value 0 0 BLKCON1 is a special function register (SFR) to make even more reducing ...
Page 52
Block Control Register 2(BLKCON2) Address: 0F02AH Access: R/W Access size: 8 bits Initial value: 00H 7 6 BLKCON2 DI2C0 ― R/W R/W R/W Initial value 0 0 BLKCON2 is a special function register (SFR) to make even more reducing ...
Page 53
Block Control Register 3(BLKCON3) Address: 0F02BH Access: R/W Access size: 8 bits Initial value: 00H 7 6 BLKCON3 ― ― R/W R/W R/W Initial value 0 0 BLKCON3 is a special function register (SFR) to make even more reducing ...
Page 54
Block Control Register 4(BLKCON4) Address: 0F02CH Access: R/W Access size: 8 bits Initial value: 00H 7 6 BLKCON4 ― DLCD R/W R/W R/W Initial value 0 0 BLKCON4 is a special function register (SFR) to make even more reducing ...
Page 55
DSAD (bit 0) The DSAD bit is used to control SA type A/D converter operation. When the DSAD bit is set to “1”, the circuits related to SA type A/D converter are reset and turned off. DSAD 0 Enable ...
Page 56
Description of Operation 4.3.1 Program Run Mode The program run mode is the state where the CPU executes instructions sequentially. At power-on reset, RESET_N pin reset, low-speed oscillation stop detect reset, or WDT overflow reset, the CPU executes instructions ...
Page 57
STOP Mode The STOP mode is the state where low-speed oscillation and high-speed oscillation stop and the CPU and peripheral circuits stop the operation. When the stop code acceptor is enabled by writing “5nH”(n: an arbitrary value) and “0AnH”(n: ...
Page 58
STOP Mode When CPU Operates with High-Speed Clock When the CPU is operating with a high-speed clock and the STP bit of SBYCON is set to “1” with the stop code acceptor enabled, the STOP mode is entered and ...
Page 59
Note on Return Operation from STOP/HALT Mode The operation of returning from the STOP mode and HALT mode varies according to the interrupt level (ELEVEL) of the program status word (PSW), master interrupt enable flag (MIE), the contents of ...
Page 60
Block Control Function This LSI has a block control function, which resets and completely turns operating circuits of unused peripherals off to make even more reducing current consumption. When certain bits of block control registers are set to “1”, ...
Page 61
Chapter 5 Interrupts (INTs) ...
Page 62
Interrupts (INTs) 5.1 Overview This LSI has 25 interrupt sources (External interrupts: 5 sources, Internal interrupts: 20 sources) and a software interrupt (SWI). For details of each interrupt, see the following chapters: Chapter 7, “Time Base Counter” Chapter 8, ...
Page 63
Description of Registers 5.2.1 List of Registers Address Name 0F011H Interrupt enable register 1 0F012H Interrupt enable register 2 0F013H Interrupt enable register 3 0F014H Interrupt enable register 4 0F015H Interrupt enable register 5 0F016H Interrupt enable register 6 ...
Page 64
Interrupt Enable Register 1 (IE1) Address: 0F011H Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ IE1 R/W R/W R/W Initial value 0 0 IE1 is a special function register (SFR) to control enable/disable for ...
Page 65
Interrupt Enable Register 2 (IE2) Address: 0F012H Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ IE2 EI2C0 R/W R/W R/W Initial value 0 0 IE2 is a special function register (SFR) to control enable/disable for ...
Page 66
Interrupt Enable Register 3 (IE3) Address: 0F013H Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ IE3 R/W R/W R/W Initial value 0 0 IE3 is a special function register (SFR) to control enable/disable for ...
Page 67
Interrupt Enable Register 4 (IE4) Address: 0F014H Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ IE4 R/W R/W R/W Initial value 0 0 IE4 is a special function register (SFR) to control enable/disable for ...
Page 68
Interrupt Enable Register 5 (IE5) Address: 0F015H Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ IE5 R/W R/W R/W Initial value 0 0 IE5 is a special function register (SFR) to control enable/disable for ...
Page 69
Interrupt Enable Register 6 (IE6) Address: 0F016H Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ IE6 E32H R/W R/W R/W Initial value 0 0 IE6 is a special function register (SFR) to control enable/disable for ...
Page 70
Interrupt Enable Register 7 (IE7) Address: 0F017H Access: R/W Access size: 8 bits Initial value: 00H 7 6 IE7 EAL1 EAL0 R/W R/W R/W Initial value 0 0 IE7 is a special function register (SFR) to control enable/disable for ...
Page 71
Interrupt Request Register 0 (IRQ0) Address: 0F018H Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ IRQ0 R/W R/W R/W Initial value 0 0 IRQ0 is a special function register (SFR) to request an interrupt ...
Page 72
Interrupt Request Register 1 (IRQ1) Address: 0F019H Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ IRQ1 R/W R/W R/W Initial value 0 0 IRQ1 is a special function register (SFR) to request an interrupt ...
Page 73
Interrupt Request Register 2 (IRQ2) Address: 0F01AH Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ IRQ2 QI2C0 R/W R/W R/W Initial value 0 0 IRQ2 is a special function register (SFR) to request an interrupt ...
Page 74
Interrupt Request Register 3 (IRQ3) Address: 0F01BH Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ IRQ3 R/W R/W R/W Initial value 0 0 IRQ3 is a special function register (SFR) to request an interrupt ...
Page 75
Interrupt Request Register 4 (IRQ4) Address: 0F01CH Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ IRQ4 R/W R/W R/W Initial value 0 0 IRQ4 is a special function register (SFR) to request an interrupt ...
Page 76
Interrupt Request Register 5 (IRQ5) Address: 0F01DH Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ IRQ5 QTM3 R/W R/W R/W Initial value 0 0 IRQ5 is a special function register (SFR) to request an interrupt ...
Page 77
Interrupt Request Register 6 (IRQ6) Address: 0F01EH Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ IRQ6 Q32H R/W R/W R/W Initial value 0 0 IRQ6 is a special function register (SFR) to request an interrupt ...
Page 78
Interrupt Request Register 7 (IRQ7) Address: 0F01FH Access: R/W Access size: 8 bits Initial value: 00H 7 6 IRQ7 QAL1 QAL0 R/W R/W R/W Initial value 0 0 IRQ7 is a special function register (SFR) to request an interrupt ...
Page 79
QAL1 (bit 7) QAL1 is the request flag for the RTC alarm 1 interrupt (AL1INT). QAL1 0 No request (initial value) 1 Request Note: When an interrupt is generated by the instruction to write to the interrupt request register ...
Page 80
Description of Operation With the exception of the watchdog timer interrupt (WDTINT) and the NMI interrupt (NMINT), interrupt enable/disable for 23 sources is controlled by the master interrupt enable flag (MIE) and the individual interrupt enable registers (IE1 to ...
Page 81
Maskable Interrupt Processing When an interrupt is generated with the MIE flag set to “1”, the following processing is executed by hardware and the processing of program shifts to the interrupt destination. (1) Transfer the program counter (PC) to ...
Page 82
Notes on Interrupt Routine Notes are different in programming depending on whether a subroutine is called or not by the program in executing an interrupt routine, whether multiple interrupts are enabled or disabled, and whether such interrupts are maskable ...
Page 83
A-2: When a subroutine is called by the program in executing an interrupt routine A-2-1: When multiple interrupts are disabled • Processing immediately after the start of interrupt routine execution Specify the “PUSH LR” instruction to save the subroutine return ...
Page 84
State B: Non-maskable interrupt is being processed B-1: When no instruction is executed in an interrupt routine • Processing immediately after the start of interrupt routine execution Specify the RTI instruction to return the contents of the ELR register to ...
Page 85
Interrupt Disable State Even if the interrupt conditions are satisfied, an interrupt may not be accepted depending on the operating state. This is called an interrupt disabled state. See below for the interrupt disabled state and the handling of ...
Page 86
Clock Generation Circuit Chapter 6 ...
Page 87
Clock Generation Circuit 6.1 Overview The clock generation circuit generates and provides a low-speed clock (LSCLK), 2× low-speed clock (LSCLK2), a high-speed clock (HSCLK), a system clock (SYSCLK), and a high-speed output clock (OUTCLK). LSCLK×2, and HSCLK are time ...
Page 88
List of Pins Pin name I/O XT0 I Pin for connecting a crystal for low-speed clock Pin for connecting a crystal for low-speed clock XT1 O Pin for connecting a crystal/ceramic resonator for high-speed clock P10/OSC0 I Used for ...
Page 89
Frequency Control Register 0 (FCON0) Address: 0F002H Access: R/W Access size: 8/16 bits Initial value: 33H 7 6 ⎯ ⎯ FCON0 R/W R/W R/W Initial value 0 0 FCON0 is a special function register (SFR) to control the high-speed ...
Page 90
Note: − To switch the mode of the high-speed clock generation circuit using the OSCM1 and OSCM0 bits, stop the high-speed oscillation and set the system clock to the low-speed clock (set the ENOSC bit and SYSCLK of FCON1 to ...
Page 91
Frequency Control Register 1 (FCON1) Address: 0F003H Access: R/W Access size: 8 bits Initial value: 03H 7 6 ⎯ FCON1 LPLL R/W R R/W Initial value 0 0 FCON1 is a special function register (SFR) to control the high-speed ...
Page 92
Description of Operation 6.3.1 Low-Speed Clock 6.3.1.1 Low-Speed Clock Generation Circuit Figure 6-2 shows the configuration of the low-speed clock generation circuit. A low-speed clock generation circuit is provided with an external 32.768 kHz crystal. To match the oscillation ...
Page 93
Operation of Low-Speed Clock Generation Circuit The low-speed clock generation circuit is activated by the occurrence of power ON reset. A low-speed clock (LSCLK) is supplied to the peripheral circuits after the elapse of the low-speed oscillation start period ...
Page 94
High-Speed Clock Setting of the OSCM1 and OSCM0 bits of the frequency control register 0 (FCON0) allows selection of the 500 kHz RC oscillation mode, crysta/ceramic oscillation mode, built-in PLL (Phase Locked Loop) oscillation mode, or external clock input ...
Page 95
Crystal/Ceramic Oscillation Mode In crystal/ceramic oscillation mode, both the P10/OSC0 pin and the P11/OSC1 pin are used for crystal ceramic oscillation. In crystal/ceramic oscillation mode, a crystal or a ceramic resonator is externally connected to the P10/OSC0 and P11/OSC1 ...
Page 96
Built-in PLL Oscillation Mode The PLL oscillation circuit generates a clock of 8.192 MHz (= 32.768 kHz × 250) ±2.5%. When the PLL oscillation clock (OSCLK) reaches within 8.192 MHz±2.5%, the LPLL flag of FCON1 is set. In built-in ...
Page 97
Operation of High-Speed Clock Generation Circuit The high-speed clock generation circuit is activated in 500Hz RC oscillation mode by power-on reset generation result of the occurrence of power-on reset, the circuit goes into system reset mode and ...
Page 98
Figure 6-9 shows the waveforms of the high-speed clock generation circuit in crystal/ceramic oscillation mode. High-speed oscillation enable ENOSC High-speed oscillation waveform High-speed clock HSCLK Low-speed clock oscillation waveform Start of high-speed oscillation Figure 6-9 Operation of High-Speed Clock Generation ...
Page 99
Switching of System Clock The system clock can be switched between high-speed clock (HSCLK) and low-speed clock (LSCLK) by using the frequency control registers (FCON0, FCON1). Figure 6-10 shows a flow of system clock switching processing (HSCLK→LSCLK) and Figure ...
Page 100
System clock switching 500 kHz RC used? Yes ENOSC←”1” Wait until oscillation stabilizes (T SYSCLK←”1” High-speed operation mode Figure 6-11 Flow of System Clock Switching Processing (LSCLK→HSCLK) Note: If the system clock is switched from a low-speed clock to a ...
Page 101
Specifying port registers When you want to make sure clock output functions are working, please check related port registers are specified. See Chapter 20, “Port2” for detail about the port registers. 6.4.1 Functioning P21 (OUTCLK) as the high speed ...
Page 102
Functioning P20 (LSCLK) as the low speed clock output Set P20MD bit (bit0 of P2MOD register) to “1” for specifying the low speed clock output as the secondary function of P22. Reg. name Bit 7 - Bit name Data ...
Page 103
Time Base Counter Chapter 7 ...
Page 104
Time Base Counter 7.1 Overview This LSI includes a low-speed time base counter (LTBC) and a high-speed time base counter (HTBC) that generate base clocks for peripheral circuits. By using the time base counter possible to generate ...
Page 105
HSCLK (4.096 MHz) RESET (Internal signal) Data bus HTBDR: High-speed time base counter frequency divide register Figure 7-2 Configuration of High-Speed Time Base Counter Note: The frequency of HSCLK changes according to specified data in SYSC1 bit and SYSC0 bit ...
Page 106
Description of Registers 7.2.1 List of Registers Address Name Low-speed time base counter 0F00AH register High-speed time base counter 0F00BH frequency divide register Low-speed time base counter 0F00CH frequency adjustment register L Low-speed time base counter 0F00DH frequency adjustment ...
Page 107
Low-Speed Time Base Counter (LTBR) Address: 0F00AH Access: R/W Access size: 8 bits Initial value: 00H 7 6 LTBR T1HZ T2HZ R/W R/W R/W Initial value 0 0 LTBR is a special function register (SFR) to read the T128HZ-T1HZ ...
Page 108
High-Speed Time Base Counter Divide Register (HTBDR) Address: 0F00BH Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ HTBDR R/W R/W R/W Initial value 0 0 HTBDR is a special function register (SFR) to set ...
Page 109
Low-Speed Time Base Counter Frequency Adjustment Registers L and H (LTBADJL, LTBADJH) Address: 0F00CH Access: R/W Access size: 8/16 bits Initial value: 00H 7 6 LTBADJL LADJ7 LADJ6 R/W R/W R/W Initial value 0 0 Address: 0F00DH Access: R/W ...
Page 110
Description of Operation 7.3.1 Low-Speed Time Base Counter The low-speed time base counter (LTBC) starts counting from 0000H on the LSCLK falling edge after system reset. The T128HZ, T32HZ, T16HZ, and T2HZ outputs of LTBC are used as time ...
Page 111
High-Speed Time Base Counter The high-speed time base counter is configured as a 4-bit 1/n counter ( 16). In the 4-bit 1/n counter, the divided clock (1/16×HSCLK to 1/1×HSCLK) selected by the high-speed time base counter ...
Page 112
Low-Speed Time Base Counter Frequency Adjustment Function Frequency adjustment (Adjustment range: Approx. −488ppm to +488ppm. Adjustment accuracy: Approx. 0.48ppm) is possible for outputs of T8KHZ to T1HZ of LTBC by using the low-speed time base counter frequency adjust registers ...
Page 113
Chapter 8 Real Time Clock ...
Page 114
Real Time Clock 8.1 Overview This LSI includes a real time clock (RTC). For input clocks, see Chapter 7, “Time Base Counter”. described in this chapter, see Chapter 5, “Interrupts”. 8.1.1 Features • Date counting function including year, month, ...
Page 115
Description of Registers 8.2.1 List of Registers Address Name Real time clock second register 0F0C0H Real time clock minute register 0F0C1H Real time clock hour register 0F0C2H Real time clock week register 0F0C3H Real time clock day register 0F0C4H ...
Page 116
Real Time Clock Second Register (RTCSEC) Address: 0F0C0H Access: R/W Access size: 8 bits Initial value: Undefined 7 6 ⎯ RTCSEC RS6 R/W R/W R/W Initial value x x RTCSEC is a special function register (SFR) to store decimal ...
Page 117
Real Time Clock Minute Register (RTCMIN) Address: 0F0C1H Access: R/W Access size: 8 bits Initial value: Undefined 7 6 ⎯ RTCMIN RM6 R/W R/W R/W Initial value x x RTCMIN is a special function register (SFR) to store decimal ...
Page 118
Real Time Clock Hour Register (RTCHOUR) Address: 0F0C2H Access: R/W Access size: 8 bits Initial value: Undefined 7 6 ⎯ ⎯ RTCHOUR R/W R/W R/W Initial value x x RTCHOUR is a special function register (SFR) to store decimal ...
Page 119
Real Time Clock Week Register (RTCWEEK) Address: 0F0C3H Access: R/W Access size: 8 bits Initial value: Undefined 7 6 ⎯ ⎯ RTCWEEK R/W R/W R/W Initial value x x RTCWEEK is a special function register (SFR) to store decimal ...
Page 120
Real Time Clock Day Register (RTCDAY) Address: 0F0C4H Access: R/W Access size: 8 bits Initial value: Undefined 7 6 ⎯ ⎯ RTCDAY R/W R/W R/W Initial value x x RTCDAY is a special function register (SFR) to store decimal ...
Page 121
Real Time Clock Month Register (RTCMON) Address: 0F0C5H Access: R/W Access size: 8 bits Initial value: Undefined 7 6 ⎯ ⎯ RTCMON R/W R/W R/W Initial value x x RTCMON is a special function register (SFR) to store decimal ...
Page 122
Real Time Clock Year Register (RTCYEAR) Address: 0F0C6H Access: R/W Access size: 8 bits Initial value: Undefined 7 6 RTCYEAR RY7 RY6 R/W R/W R/W Initial value x x RTCYEAR is a special function register (SFR) to store decimal ...
Page 123
Real Time Clock Control Register (RTCCON) Address: 0F0C7H Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ RTCCON R/W R/W R/W Initial value 0 0 RTCCON is a special function register (SFR) to control the ...
Page 124
Real Time Clock Alarm 0 Minute Register (AL0MIN) Address: 0F0C8H Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ AL0MIN AL0M6 R/W R/W R/W Initial value 0 0 AL0MIN is a special function register (SFR) to ...
Page 125
Real Time Clock Alarm 0 Hour Register (AL0HOUR) Address: 0F0C9H Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ AL0HOUR R/W R/W R/W Initial value 0 0 AL0HOUR is a special function register (SFR) to ...
Page 126
Real Time Clock Alarm 0 Week Register (AL0WEEK) Address: 0F0CAH Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ AL0WEEK R/W R/W R/W Initial value 0 0 AL0WEEK is a special function register (SFR) to ...
Page 127
Real Time Clock Alarm 1 Minute Register (AL1MIN) Address: 0F0CBH Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ AL1MIN AL1M6 R/W R/W R/W Initial value 0 0 AL1MIN is a special function register (SFR) to ...
Page 128
Real Time Clock Alarm 1 Hour Register (AL1HOUR) Address: 0F0CCH Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ AL1HOUR R/W R/W R/W Initial value 0 0 AL1HOUR is a special function register (SFR) to ...
Page 129
Real Time Clock Alarm 1 Day Register (AL1DAY) Address: 0F0CDH Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ AL1DAY R/W R/W R/W Initial value 0 0 AL1DAY is a special function register (SFR) to ...
Page 130
Real Time Clock Alarm 1 Month Register (AL1MON) Address: 0F0CEH Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ AL1MON R/W R/W R/W Initial value 0 0 AL1MON is a special function register (SFR) to ...
Page 131
Description of Operation RTC stops operation after reset release. As each bit of the date and time registers ((RTCSEC, RTCMIN, RTCHOUR, RTCWEEK, RTCDAY, RTCMON, and RTCYEAR) is undefined, set a date and a time through the software. Set a ...
Page 132
An alarm 0 interrupt (AL0INT) occurs when carry (RTCSEC: 59 seconds→00 seconds) from the second register (RTCSEC) occurs and the value of the real time clock alarm 0 register (AL0WEEK, AL0HOUR, or AL0MIN) and the value of the day of ...
Page 133
Chapter 9 Capture ...
Page 134
Capture 9.1 Overview This LSI has two channels of capture circuits that capture the T4KHZ to T32HZ signals of the low-speed base counter (LTBC) to the capture register at the occurrence of P00 and P01 interrupts. The circuits capture ...
Page 135
Description of Registers 9.2.1 List of Registers Address Name 0F090H Capture control register 0F091H Capture status register 0F092H Capture data register 0 0F093H Capture data register 1 ML610Q431/ML610Q432 User’s Manual Symbol (Byte) Symbol (Word) ⎯ CAPCON ⎯ CAPSTAT ⎯ ...
Page 136
Capture Control Register (CAPCON) Address: 0F090H Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ CAPCON R/W R/W R/W Initial value 0 0 CAPCON is a special function register (SFR) to control the capture circuit. ...
Page 137
Capture Status Register (CAPSTAT) Address: 0F091H Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ CAPSTAT R/W R/W R/W Initial value 0 0 CAPSTAT is a special function register (SFR) to indicate a state of ...
Page 138
Capture Data Register 0 (CAPR0) Address: 0F092H Access: R/W Access size: 8 bits Initial value: 00H 7 6 CAPR0 CP07 CP06 R/W R/W R/W Initial value 0 0 CAPR0 is a register in which capture data is stored. The ...
Page 139
Capture Data Register 1 (CAPR1) Address: 0F093H Access: R/W Access size: 8 bits Initial value: 00H 7 6 CAPR1 CP17 CP16 R/W R/W R/W Initial value 0 0 CAPR1 is a register in which capture data is stored. The ...
Page 140
Description of Operation The capture circuit starts the capture operation by setting the ECAP0 or ECAP1 bit of the capture control register (CAPCON). When the input trigger from the P00 or P01 pin selected by the external interrupt control ...
Page 141
Timer (1kHzTM) Chapter 10 ...
Page 142
Timer (1kHzTM) 10.1 Overview This LSI includes a 1 kHz timer to measure 1/1000 seconds. The 1 kHz timer counts the 1 kHz signal created by dividing the T2KHZ output frequency (2.048 kHz) of the low-speed time ...
Page 143
Description of Registers 10.2.1 List of Registers Address Name 0F080H 1 kHz timer count register L 0F081H 1 kHz timer count register H 0F082H 1 kHz timer control register ML610Q431/ML610Q432 User’s Manual Chapter 10 1 kHz Timer (1kHzTM) Symbol ...
Page 144
Timer Count Registers (T1KCRL, T1KCRH) Address: 0F080H Access: R/W Access size: 8/16 bits Initial value: 00H 7 6 T1KCRL T1KC3 T1K02 R/W R/W R/W Initial value 0 0 Address: 0F081H Access: R/W Access size: 8 bits Initial ...
Page 145
Timer Control Register (T1KCON) Address: 0F082H Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ T1KCON R/W R/W R/W Initial value 0 0 T1KCON is a special function register (SFR) to control the ...
Page 146
Description of Operation By setting the T1KRUN bit of the 1kHz timer control register (T1KCON) to “1”, the 1kHz timer starts counting of the 1kHz timer counter registers (T1KCRL, T1KCRH). By dividing the T2KHz signal frequency ...
Page 147
Chapter 11 Timers ...
Page 148
Timers 11.1 Overview This LSI includes 4 channels of 8-bit timers. For the input clock, see Chapter 6, “Clock Generation Circuit”. 11.1.1 Features • The timer interrupt (TMnINT) is generated when the values of timer counter register (TMnC, n=0 ...
Page 149
Description of Registers 11.2.1 List of Registers Address Name Timer 0 data register 0F030H 0F031H Timer 0 counter register Timer 0 control register 0 0F032H Timer 0 control register 1 0F033H Timer 1 data register 0F034H 0F035H Timer 1 ...
Page 150
Timer 0 Data Register (TM0D) Address: 0F030H Access: R/W Access size: 8 bits Initial value: 0FFH 7 6 TM0D T0D7 T0D6 R/W R/W R/W Initial value 1 1 TM0D is a special function register (SFR) to set the value ...
Page 151
Timer 1 Data Register (TM1D) Address: 0F034H Access: R/W Access size: 8 bits Initial value: 0FFH 7 6 TM1D T1D7 T1D6 R/W R/W R/W Initial value 1 1 TM1D is a special function register (SFR) to set the value ...
Page 152
Timer 2 Data Register (TM2D) Address: 0F038H Access: R/W Access size: 8 bits Initial value: 0FFH 7 6 TM2D T2D7 T2D6 R/W R/W R/W Initial value 1 1 TM2D is a special function register (SFR) to set the value ...
Page 153
Timer 3 Data Register (TM3D) Address: 0F03CH Access: R/W Access size: 8 bits Initial value: 0FFH 7 6 TM3D T3D7 T3D6 R/W R/W R/W Initial value 1 1 TM3D is a special function register (SFR) to set the value ...
Page 154
Timer 0 Counter Register (TM0C) Address: 0F031H Access: R/W Access size: 8 bits Initial value: 00H 7 6 TM0C T0C7 T0C6 R/W R/W R/W Initial value 0 0 TM0C is a special function register (SFR) that functions as an ...
Page 155
Timer 1 Counter Register (TM1C) Address: 0F035H Access: R/W Access size: 8 bits Initial value: 00H 7 6 TM1C T1C7 T1C6 R/W R/W R/W Initial value 0 0 TM1C is a special function register (SFR) that functions as an ...
Page 156
Timer 2 Counter Register (TM2C) Address: 0F039H Access: R/W Access size: 8 bits Initial value: 00H 7 6 TM2C T2C7 T2C6 R/W R/W R/W Initial value 0 0 TM2C is a special function register (SFR) that functions as an ...
Page 157
Timer 3 Counter Register (TM3C) Address: 0F03DH Access: R/W Access size: 8 bits Initial value: 00H 7 6 TM3C T3C7 T3C6 R/W R/W R/W Initial value 0 0 TM3C is a special function register (SFR) that functions as an ...
Page 158
Timer 0 Control Register 0 (TM0CON0) Address: 0F032H Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ TM0CON0 R/W R/W R/W Initial value 0 0 TM0CON0 is a special function (SFR) to control a timer ...
Page 159
Timer 1 Control Register 0 (TM1CON0) Address: 0F036H Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ TM1CON0 R/W R/W R/W Initial value 0 0 TM1CON0 is a special function (SFR) to control a timer ...
Page 160
Timer 2 Control Register 0 (TM2CON0) Address: 0F03AH Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ TM2CON0 R/W R/W R/W Initial value 0 0 TM2CON0 is a special function (SFR) to control a timer ...
Page 161
Timer 3 Control Register 0 (TM3CON0) Address: 0F03EH Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ TM3CON0 R/W R/W R/W Initial value 0 0 TM3CON0 is a special function (SFR) to control a timer ...
Page 162
Timer 0 Control Register 1 (TM0CON1) Address: 0F033 Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ TM0CON1 T0STAT R/W R R/W Initial value 0 0 TM0CON1 is a special function register (SFR) to control a ...
Page 163
Timer 1 Control Register 1 (TM1CON1) Address: 0F037H Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ TM1CON1 T1STAT R/W R R/W Initial value 0 0 TM1CON1 is a special function register (SFR) to control a ...
Page 164
Timer 2 Control Register 1 (TM2CON1) Address: 0F03BH Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ TM2CON1 T2STAT R/W R R/W Initial value 0 0 TM2CON1 is a special function register (SFR) to control a ...
Page 165
Timer 3 Control Register 1 (TM3CON1) Address: 0F03FH Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ TM3CON1 T3STAT R/W R R/W Initial value 0 0 TM3CON1 is a special function register (SFR) to control a ...
Page 166
Description of Operation The timer counters (TMnC) are set to an operating state (TnSTAT are set to “1”) on the first falling edge of the timer clocks (TnCK) that are selected by the Timer control register ...
Page 167
Chapter 12 PWM ...
Page 168
PWM 12.1 Overview This LSI includes one channel of 16-bit PWM (Pulse Width Modulation). The PWM output (PWM0) function is assigned to P43(Port 4) and P34(Port 3) as the tertiary function. For the functions of port 4 and port3, ...
Page 169
List of Pins Pin name I/O P43/PWM0 O P34/PWM0 O 12.2 Description of Registers 12.2.1 List of Registers Address Name 0F0A0H PWM0 period register L PWM0 period register H 0F0A1H PWM0 duty register L 0F0A2H 0F0A3H PWM0 duty register ...
Page 170
PWM0 Period Registers (PW0PL, PW0PH) Address: 0F0A0H Access: R/W Access size: 8 bits Initial value: 0FFH 7 6 PW0PL P0P7 P0P6 R/W R/W R/W At reset 1 1 Address: 0F0A1H Access: R/W Access size: 8 bits Initial value: 0FFH ...
Page 171
PWM0 Duty Registers (PW0DL, PW0DH PW0DL P0D7 P0D6 R/W R/W R/W At reset 0 0 Address: 0F0A2H Access: R/W Access size: 8 bits Initial value: 00H 7 6 PW0DH P0D15 P0D14 R/W R/W R/W At reset 0 ...
Page 172
PWM0 Counter Registers (PW0CH, PW0CL PW0CL P0C7 P0C6 R/W R/W R/W At reset 0 0 Address: 0F0A4H Access: R/W Access size: 8 bits Initial value: 00H 7 6 PW0DH P0C15 P0C14 R/W R/W R/W At reset 0 ...
Page 173
PWM0 Control Register 0 (PW0CON0 ⎯ ⎯ PW0CON0 R/W R/W R/W At reset 0 0 Address: 0F0A6H Access: R/W Access size: 8 bits Initial value: 00H PW0CON0 is a special function register (SFR) to control PWM. [Description ...
Page 174
PWM0 Control Register 1 (PW0CON1 PW0CON1 P0STAT P0FLG R/W R R/W At reset 0 1 Address: 0F0A7H Access: R/W Access size: 8 bits Initial value: 40H PW0CON1 is a special function register (SFR) to control PWM0. [Description ...
Page 175
Description of Operation The PWM0 counter registers (PW0CH, PW0CL) are set to an operating state (P0STAT is set to “1”) on the first falling edge of the PWM clock (P0CK) that are selected by the PWM0 control register 0 ...
Page 176
After the P0RUN bit is set to “1”, counting starts in synchronization with the PWM clock. This causes an error clock pulse to the time the first PWM interrupt is issued. The PWM interrupt period from ...
Page 177
Specifying port registers When you want to make sure the PWM function is working, please check related port registers are specified. See Chapter 22, “Port 4” and Chapter 21, “Port 3” for detail about the port registers. 12.4.1 Functioning ...
Page 178
Functioning P34 (PWM0) as the PWM output Set P34MD1 bit (bit4 of P3MOD1 register) to “1” and set P34MD0 bit (bit4 of P3MOD0 register) to “0”, for specifying the PWM output as the tertiary function of P34. Reg. name ...
Page 179
Chapter 13 Watchdog Timer ...
Page 180
Watchdog Timer 13.1 Overview This LSI incorporates a watchdog timer (WDT) that operates at a system reset unconditionally (free-run operation) in order to detect an undefined state of the MCU and return from that state. If the WDT counter ...
Page 181
Description of Registers 13.2.1 List of Registers Address Name 0F00EH Watchdog timer control register 0F00FH Watchdog timer mode register ML610Q431/ML610Q432 User’s Manual Chapter 13 Watchdog Timer Symbol (Byte) Symbol (Word) ⎯ WDTCON ⎯ WDTMOD 13 – 2 R/W Size ...
Page 182
Watchdog Timer Control Register (WDTCON) Address: 0F00EH Access: W Access size: 8 bits Initial value: 00H 7 6 WDTCON d7 d6 R/W R/W R/W Initial value 0 0 WDTCON is a special function register (SFR) to clear the WDT ...
Page 183
Watchdog Timer Mode Register (WDTMOD) Address: 0F00FH Access: W Access size: 8 bits Initial value: 02H 7 6 ⎯ ⎯ WDTMOD R/W R/W R/W Initial value 0 0 WDTMOD is a special function register to set the overflow period ...
Page 184
Description of Operation The WDT counter starts counting after the system reset has been released and the low-speed clock oscillation start.. Write "5AH" when the internal pointer (WDP) is "0"and then the WDT counter is cleared by writing "0A5H" ...
Page 185
Figure 13-2 shows an example of watchdog timer operation. Low-speed oscillation start RESET_S System reset Data: WDTCON Write WDTP Internal pointer WDT counter WDTINT WDT interrupt WDT reset Figure 13-2 Example of Watchdog Timer Operation 1 The WDT counter starts ...
Page 186
Handling example when you do not want to use the watchdog timer WDT counter is a free-run counter that starts count-up automatically after the system reset released and the low-speed clock (LSCLK) starts oscillating. If the WDT counter gets ...
Page 187
Synchronous Serial Port Chapter 14 ...
Page 188
Synchronous Serial Port 14.1 Overview This LSI includes one channel of the 8/16-bit synchronous serial port (SSIO) and can also be used to control the device incorporated with the SPI interface by using one GPIO as the chip enable ...
Page 189
List of Pins Pin name I/O P40/SIN0 I P44/SIN0 P41/SCK0 I/O P45/SCK0 P42/SOUT0 O P46/SOUT0 Description Receive data input. Used for the tertiary function of the P40 and P44 pins. Synchronous clock input/output. Used for the tertiary function of ...
Page 190
Description of Registers 14.2.1 List of Registers Address Name Serial port 0 transmit/receive 0F280H buffer L Serial port 0 transmit/receive 0F281H buffer H Serial port 0 control register 0F282H Serial port 0 mode register 0 0F284H 0F285H Serial port ...
Page 191
Serial Port Transmit/Receive Buffers (SIO0BUFL, SIO0BUFH) Address: 0F280H Access: R/W Access size: 8 bits/16 bits Initial value: 00H 7 6 SIO0BUFL S0B7 S0B6 R/W R/W R/W Initial value 0 0 Address: 0F281H Access: R/W Access size: 8 bits Initial ...
Page 192
Serial Port Control Register (SIO0CON) Address: 0F282H Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ SIO0CON R/W R/W R/W Initial value 0 0 SIO0CON is a special function register (SFR) to control the synchronous ...
Page 193
Serial Port Mode Register 0 (SIO0MOD0) Address: 0F284H Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ SIO0MOD0 R/W R/W R/W Initial value 0 0 SIO0MOD0 is a special function register (SFR) to set mode ...
Page 194
Serial Port Mode Register 1 (SIO0MOD1) Address: 0F285H Access: R/W Access size: 8 bits Initial value: 00H 7 6 ⎯ ⎯ SIO0MOD1 R/W R/W R/W Initial value 0 0 SIO0MOD1 is a special function register (SFR) to set mode ...
Page 195
Description of Operation 14.3.1 Transmit Operation When “1” is written to the S0MD1 bit and “0” is written to the S0MD0 bit of the serial mode register (SIO0MOD0), this LSI is set to a transmit mode. When transmit data ...
Page 196
Receive Operation When “0” is written to the S0MD1 bit and “1” is written to the S0MD0 bit of the serial mode register (SIO0MOD0), this LSI is set to a receive mode. When the S0EN bit of the serial ...
Page 197
Transmit/Receive Operation When “1” is written to the S0MD1 bit and “1” is written to the S0MD0 bit of the serial mode register (SIO0MOD0), this LSI is set to a transmit/receive mode. When the S0EN bit of the serial ...
Page 198
Specifying port registers When you want to make sure the SSIO function is working, please check related port registers are specified. See Chapter 22, “Port 4” for detail about the port registers. 14.4.1 Functioning P42 (SOUT0), P41 (SCK0) and ...
Page 199
Functioning P42 (SOUT0), P41 (SCK0) and P40 (SIN0) as the SSIO/ ”Slave mode” Set P42MD1-P40MD1 bits(bit2-bit0 of P4MOD1 register) to “1” and set P42MD0-P40MD0(bit2-bit0 of P4MOD0 register) to “0”, for specifying the SSIO as the secondary function of P42, ...
Page 200
Functioning P46 (SOUT0), P45 (SCK0) and P44 (SIN0) as the SSIO/ ”Master mode” Set P46MD1-P44MD1 bits(bit6-bit4 of P4MOD1 register) to “1” and set P46MD0-P44MD0(bit6-bit4 of P4MOD0 register) to “0”, for specifying the SSIO as the secondary function of P46, ...