ML610Q432A-NNNTC03A7 Rohm Semiconductor, ML610Q432A-NNNTC03A7 Datasheet - Page 196
ML610Q432A-NNNTC03A7
Manufacturer Part Number
ML610Q432A-NNNTC03A7
Description
MCU 8BIT 64K FLASH 128-TQFP
Manufacturer
Rohm Semiconductor
Datasheets
1.ML610Q482P-NNNTB03A7.pdf
(20 pages)
2.ML610Q432A-NNNTC03A7.pdf
(35 pages)
3.ML610Q432A-NNNTC03A7.pdf
(458 pages)
Specifications of ML610Q432A-NNNTC03A7
Core Processor
nX-U8/100
Core Size
8-Bit
Speed
4.2MHz
Connectivity
I²C, SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 2x12b, 2x24b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
ML610Q432A-NNNTC03A7
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Quantity:
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14.3.2
When “0” is written to the S0MD1 bit and “1” is written to the S0MD0 bit of the serial mode register (SIO0MOD0),
this LSI is set to a receive mode.
When the S0EN bit of the serial port control register (SIO0CON) is set to “1”, reception starts. When reception of
8/16-bit data terminates, a synchronous serial port interrupt (SIO0INT) occurs and the S0EN bit is set to “0”.
Receive data is input from the tertiary function pins (P40/SIN0 or P44/SIN0) of GPIO.
When an internal clock is selected in the serial port mode register (SIO0MD1), the LSI is set to a master mode and
when an external clock (P41/SCK0 or P45/SCK0) is selected, the LSI is set to a slave mode.
The serial port mode register (SIO0MOD0) enables selection of MSB first or LSB first.
The receive data input pin (P40/SIN0 or P44/SIN0) and transfer clock input/output pin (P41/SCK0 or P45/SCK0) must
be set to the tertiary function.
Figures 14-4 and 14-5 show the receive operation waveforms of the synchronous serial ports for clock type 0 and clock
type 1, respectively (8-bit length, MSB first, clock types 0 and 1).
Note:
When the SOUT0 pin is set to the tertiary function output in receive mode, a “H” level is output from the SOUT0
output pin.
Receive Operation
Shift register
Shift register
SIO0RCL
SIO0RCL
SIO0INT
SIO0INT
Figure 14-4 Receive Operation Waveforms of Synchronous Serial Port
Figure 14-5 Receive Operation Waveforms of Synchronous Serial Port
S0EN
SCK0
S0EN
SCK0
SIN0
SIN0
for Clock Type 0 (8-bit Length, MSB first)
for Clock Type 1 (8-bit Length, MSB first)
7
7
7
7
6
6
6
6
5
5
14 – 9
5
5
4
4
4
4
3
3
ML610Q431/ML610Q432 User’s Manual
3
3
2
2
Chapter 14 Synchronous Serial Port
2
2
1
1
1
1
0
0
Receive data
0
Receive data
0
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