ML610Q435A-NNNTC03A7 Rohm Semiconductor, ML610Q435A-NNNTC03A7 Datasheet - Page 351

• Manufacturer Part Number: ML610Q435A-NNNTC03A7
• Description: MCU 8BIT 96K FLASH 144-LQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q435A-NNNTC03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 96KB (48K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

26.2.6
• SALP (bit 0)
• SACK (bit 1)
Address: 0F2F0H
Access: R/W
Access size: 8/16 bits
Initial value: 02H
SADCON0 is a special function register (SFR) used to control the operation of the SA-ADC.
[Description of Bits]
This bit is used to select whether A/D conversion is performed once only for each channel or consecutively. When this
bit is set to “0”, A/D conversion is performed once only for each channel and when it is set to “1”, A/D conversion is
performed consecutively according to the settings of the amplifier control register 0 (AMPCON0) and SA-ADC mode
register (SADMOD0).
Notes:
When amplification input or differential amplification input is selected by amplifier control register 0, the amplifier
settling time is required before starting A/D conversion. So set the SALP bit to “0” without using the setting of
“Consecutive A/D conversion”.
Set the SALP bit when the SARUN bit of the SADCON1 register is “0” (A/D conversion inactive).
Use the SADMOD0 register to select a channel. See Section 26.3.2, A/D Conversion Channel Settings, for the details.
The SACK bit is used to set an A/D conversion time.
As a conversion time is set by counting HSCLK, set this bit to “0” when HSCLK is set in the range of 375kHz to
625kHz and when HSCLK is set in the range of 1.5MHz to 4.2MHz, set this bit to “1”.
Note:
Set the SACK bit when the SARUN bit of the SADCON1 register is “0” (A/D conversion inactive).
SA-ADC is available only when VDD=1.8V to 3.6V and HSCLK is in the ranges of 375KHz to 625kHz and of
1.5MHz to 4.2MHz.
Initial value
SADCON0
R/W
SACK
SALP
0
1
0
1
SA-ADC Control Register 0 (SADCON0)
R/W
Single A/D conversion only (Initial value)
Consecutive A/D conversion
HSCLK is set to the range of 375kHz to 625kHz.
HSCLK is set to the range of 1.5MHz to 4.2MHz (Initial value)
⎯
7
0
R/W
⎯
6
0
R/W
⎯
5
0
Chapter 26 Successive Approximation Type A/D Converter
Description
Description
R/W
⎯
4
0
26 – 6
R/W
⎯
3
0
ML610Q435/ML610Q436 User’s Manual
R/W
⎯
2
0
SACK
R/W
1
0
SALP
R/W
0
0