ML610Q435A-NNNTC03A7 Rohm Semiconductor, ML610Q435A-NNNTC03A7 Datasheet - Page 57

• Manufacturer Part Number: ML610Q435A-NNNTC03A7
• Description: MCU 8BIT 96K FLASH 144-LQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q435A-NNNTC03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 96KB (48K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.3
4.3.1
4.3.2
The program run mode is the state where the CPU executes instructions sequentially.
At power-on reset, RESET_N pin reset, low-speed oscillation stop detect reset, or WDT overflow reset, the CPU
executes instructions from the addresses that are set in addresses 0002H and 0003H of program memory (ROM) after
the system reset mode is released.
At reset by the BRK instruction, the CPU executes instructions from the addresses that are set in the addresses 0004H
and 0005H of the program memory after the system reset mode is released. However, when the value of the interrupt
level bit (ELEVEL) of the program status word (PSW) is 02H or higher at execution of the BRK instruction (after the
occurrence of the WDT interrupt or NMI interrupt), the CPU executes instructions from the addresses that are set in the
addresses 0002H and 0003H.
For details of the BRK instruction and PSW, see the “nX-U8/100 Core Instruction Manual” and for the reset function,
see Chapter 3, “Reset Function”.
The HALT mode is the state where the CPU interrupts execution of instructions and only the peripheral circuits are
running.
When the HLT bit of the standby control register (SBYCON) is set to “1”, the HALT mode is set.
When a NMI interrupt request, a WDT interrupt request, or an interrupt request enabled by an interrupt enable register
(IE1–IE7) is issued, the HLT bit is set to “0” on the falling edge of the next system clock (SYSCLK) and the HALT
mode is returned to the program run mode released.
Figure 4-2 shows the operation waveforms in HALT mode.
Note:
Since up to two instructions are executed during the period between HALT mode release and a transition to interrupt
processing, place two NOP instructions next to the instruction that sets the HLT bit to “1”.
Description of Operation
Program Run Mode
HALT Mode
Interrupt request
SBYCON.HLT
System clock
CPUCLK
SYSCLK
Program operating mode
Figure 4-2 Operation Waveforms in HALT Mode
4 – 11
HALT mode
ML610Q435/ML610Q436 User’s Manual
Chapter 4 MCU Control Function
Program operating mode