FSDM0565RELDTU Fairchild Semiconductor, FSDM0565RELDTU Datasheet - Page 12

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FSDM0565RELDTU

Manufacturer Part Number
FSDM0565RELDTU
Description
IC PWM/SENSEFET 650V TO-220F-6
Manufacturer
Fairchild Semiconductor
Series
FPS™r
Datasheet

Specifications of FSDM0565RELDTU

Output Isolation
Isolated
Frequency Range
60kHz ~ 72kHz
Voltage - Input
9 V ~ 20 V
Voltage - Output
650V
Power (watts)
70W
Operating Temperature
-25°C ~ 85°C
Package / Case
TO-220-6 Full Pack Formed Leads
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
FSDM0465RE, FSDM0565RE, FSDM07652RE Rev. 1.0.2
© 2006 Fairchild Semiconductor Corporation
Functional Description
1. Start-up: In previous generations of Fairchild Power
Switches (FPS™), the V
resistor to the DC input voltage line. In this generation,
the start-up resistor is replaced by an internal high-
voltage current source. At start-up, the internal high-
voltage current source supplies the internal bias and
charges the external capacitor (C
V
12V, the FSDM0x65RE begins switching and the internal
high-voltage
FSDM0x65RE continues normal switching operation and
the power is supplied from the auxiliary transformer
winding unless V
2. Feedback Control: FSDM0x65RE employs current-
mode control, as shown in Figure 18. An opto-coupler
(such as the H11A817A) and shunt regulator (such as
the KA431) are typically used to implement the feedback
network. Comparing the feedback voltage with the
voltage across the R
makes it possible to control the switching duty cycle.
When the reference pin voltage of the shunt regulator
exceeds the internal reference voltage of 2.5V, the opto-
coupler LED current increases, pulling down the
feedback voltage and reducing the duty cycle. This event
typically occurs when the input voltage is increased or
the output load is decreased.
CC
pin, as illustrated in Figure 17. When V
8V/12V
Figure 17. Internal Start-up Circuit
V
CC
3
current
CC
goes below the stop voltage of 8V.
sense
C
CC
Vcc
source
resistor, plus an offset voltage,
V
CC
pin had an external start-up
good
vcc
is
) connected to the
FSDM0565RE Rev: 00
disabled.
I
start
Internal
Vref
Bias
CC
V
6
DC
reaches
V
str
The
12
2.1 Pulse-by-Pulse Current Limit: Because current-
mode control is employed, the peak current through the
SenseFET is limited by the inverting input of PWM
comparator (V
the 0.9mA current source flows only through the internal
resistor (2.5R + R = 2.8kΩ), the cathode voltage of diode
D2 is about 2.5V. Since D1 is blocked when the feedback
voltage (V
cathode of D2 is clamped at this voltage, thus clamping
V
the SenseFET is limited.
2.2 Leading Edge Blanking (LEB): At the instant the
internal SenseFET is turned on, a high-current spike
occurs through the SenseFET, caused by primary-side
capacitance
recovery. Excessive voltage across the R
would lead to incorrect feedback operation in the current
mode PWM control. To counter this effect, the
FSDM0x65RE employs a leading-edge blanking (LEB)
circuit. This circuit inhibits the PWM comparator for a
short time (t
3. Protection Circuit: The FSDM0x65RE has several
self-protective functions, such as overload protection
(OLP), over-voltage protection (OVP), and thermal
shutdown (TSD). Because these protection circuits are
fully integrated into the IC without external components,
the reliability is improved without increasing cost. Once a
fault condition occurs, switching is terminated and the
SenseFET remains off, which causes V
V
is reset and the internal high-voltage current source
charges the V
reaches
FSDM0x65RE resumes normal operation. In this
manner, the auto-restart can alternately enable and
disable the switching of the power SenseFET until the
fault condition is eliminated (see Figure 19).
V
FSDM0565RE Rev: 00
FB
CC
O
Figure 18. Pulse-Width-Modulation (PWM) Circuit
*. Therefore, the peak value of the current through
reaches the UVLO stop voltage of 8V, the protection
H11A817A
KA431
FB
the
LEB
) exceeds 2.5V, the maximum voltage of the
V
FB
FB
and
CC
) after the SenseFET is turned on.
UVLO
*) as shown in Figure 18. Assuming that
C
B
capacitor via the V
4
I
delay
V
secondary-side
V
SD
CC
D1
start
V
ref
I
V
FB
D2
+
fb
-
*
voltage
2.5R
R
OSC
str
rectifier
OLP
CC
pin. When V
of
sense
www.fairchildsemi.com
driver
to fall. When
Gate
12V,
R
SenseFET
sense
reverse
resistor
the
CC

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