AT32UC3L0-XPLD Atmel, AT32UC3L0-XPLD Datasheet - Page 20

• Manufacturer Part Number: AT32UC3L0-XPLD
• Description: KIT DEV/EVAL FOR AT32UC3L0
• Manufacturer: Atmel

Specifications of AT32UC3L0-XPLD

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3.1
32099F–11/2010
Pipeline Overview
Figure 4-1.
AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc-
tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic
(ALU) section, one multiply (MUL) section, and one load/store (LS) section.
Instructions are issued and complete in order. Certain operations require several clock cycles to
complete, and in this case, the instruction resides in the ID and EX stages for the required num-
ber of clock cycles. Since there is only three pipeline stages, no internal data forwarding is
required, and no data dependencies can arise in the pipeline.
Figure 4-2 on page 21
Instruction memory controller
High Speed Bus master
Overview of the AVR32UC CPU
system
shows an overview of the AVR32UC pipeline stages.
OCD
AVR32UC CPU pipeline
High Speed
Bus master
MPU
Data memory controller
Bus slave
Speed
AT32UC3L016/32/64
High
CPU Local
Power/
control
Reset
master
Bus
CPU RAM
20