AT32UC3L0-XPLD Atmel, AT32UC3L0-XPLD Datasheet - Page 34
AT32UC3L0-XPLD
Manufacturer Part Number
AT32UC3L0-XPLD
Description
KIT DEV/EVAL FOR AT32UC3L0
Manufacturer
Atmel
Datasheet
1.AT32UC3L016-D3HT.pdf
(110 pages)
Specifications of AT32UC3L0-XPLD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Table 5-3.
5.4
32099F–11/2010
CPU Local Bus Mapping
Peripheral Address Mapping
0xFFFF4C00
0xFFFF5C00
0xFFFF6C00
0xFFFF4800
0xFFFF5000
0xFFFF5400
0xFFFF5800
0xFFFF6000
0xFFFF6400
0xFFFF6800
0xFFFF7000
Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to
being mapped on the Peripheral Bus. These registers can therefore be reached both by
accesses on the Peripheral Bus, and by accesses on the local bus.
Mapping these registers on the local bus allows cycle-deterministic toggling of GPIO pins since
the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at
CPU speed, one write or read operation can be performed per clock cycle to the local bus-
mapped GPIO registers.
ADCIFB
TWIM1
TWIS0
TWIS1
PWMA
ACIFB
GLOC
TC0
TC1
CAT
AW
Two-wire Master Interface - TWIM1
Two-wire Slave Interface - TWIS0
Two-wire Slave Interface - TWIS1
Pulse Width Modulation Controller - PWMA
Timer/Counter - TC0
Timer/Counter - TC1
ADC Interface - ADCIFB
Analog Comparator Interface - ACIFB
Capacitive Touch Module - CAT
Glue Logic Controller - GLOC
aWire - AW
AT32UC3L016/32/64
34
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