AT32UC3L0-XPLD Atmel, AT32UC3L0-XPLD Datasheet - Page 71

• Manufacturer Part Number: AT32UC3L0-XPLD
• Description: KIT DEV/EVAL FOR AT32UC3L0
• Manufacturer: Atmel

Specifications of AT32UC3L0-XPLD

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 7-42.
Notes:
32099F–11/2010
t
t
t
t
t
f
SU-DAT-TWI
SU-DAT
LOW-TWI
LOW
HIGH
TWCK
Symbol
1. Standard mode:
2. A device must internally provide a hold time of at least 300 ns for TWD with reference to the falling edge of TWCK.
Data set-up time
TWCK LOW period
TWCK HIGH period
TWCK frequency
TWI-Bus Timing Requirements
Parameter
Notations:
C
t
t
The maximum t
of TWCK.
f
clkpb
prescaled
TWCK
b
= total capacitance of one bus line in pF
= period of TWI peripheral bus clock
≤
100 kHz
= period of TWI internal prescaled clock (see chapters on TWIM and TWIS)
Standard
Fast
-
Standard
Fast
-
Standard
Fast
Standard
Fast
; fast mode:
HD;DAT
Mode
has only to be met if the device does not stretch the LOW period (t
Requirement
f
TWCK
250
100
4.7
1.3
4.0
0.6
-
-
>
100 kHz
Minimum
-
.
Device
2t
4t
8t
t
t
clkpb
clkpb
clkpb
clkpb
clkpb
AT32UC3L016/32/64
Requirement
100
400
Maximum
-
-
-
-
-
----------------------- -
12t clkpb
Device
1
LOW-TWI
Unit
kHz
μs
μs
ns
-
-
71
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