EP3C10M164C8N Altera, EP3C10M164C8N Datasheet - Page 47
EP3C10M164C8N
Manufacturer Part Number
EP3C10M164C8N
Description
IC CYCLONE III FPGA 402MHZ BGA-164
Manufacturer
Altera
Series
Cyclone IIIr
Specifications of EP3C10M164C8N
No. Of Logic Blocks
645
Family Type
Cyclone III
No. Of I/o's
106
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Family Name
Cyclone III
Number Of Logic Blocks/elements
10320
# I/os (max)
106
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
10320
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
164
Package Type
MBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Chapter 3: Memory Blocks in the Cyclone III Device Family
Memory Modes
Figure 3–10. Cyclone III Device Family Simple Dual-Port Timing Waveforms
True Dual-Port Mode
© December 2009
q (asynch)
wraddress
rdaddress
wrclock
rdclock
wren
data
rden
1
Altera Corporation
din-1
doutn-1
an-1
Figure 3–10
dual-port mode with unregistered outputs. Registering the outputs of the RAM
simply delays the q output by one clock cycle.
True dual-port mode supports any combination of two-port operations: two reads,
two writes, or one read and one write, at two different clock frequencies.
shows the Cyclone III device family true dual-port memory configuration.
Figure 3–11. Cyclone III Device Family True Dual-Port Memory
Note to
(1) True dual-port memory supports input or output clock mode in addition to the independent clock mode shown.
The widest bit configuration of the M9K blocks in true dual-port mode is 512 × 16-bit
(18-bit with parity).
bn
Figure
an
din
3–11:
shows the timing waveforms for read and write operations in simple
doutn
b0
a0
a1
data_a[ ]
address_a[ ]
wren_a
byteena_a[]
addressstall_a
clocken_a
rden_a
aclr_a
q_a[]
clock_a
dout0
a2
b1
a3
addressstall_b
address_b[]
byteena_b[]
clocken_b
data_b[ ]
clock_b
wren_b
rden_b
aclr_b
q_b[]
din4
b2
a4
(Note 1)
Cyclone III Device Handbook, Volume 1
din5
a5
b3
a6
din6
Figure 3–11
3–11
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