EP3C10M164C8N Altera, EP3C10M164C8N Datasheet - Page 94
EP3C10M164C8N
Manufacturer Part Number
EP3C10M164C8N
Description
IC CYCLONE III FPGA 402MHZ BGA-164
Manufacturer
Altera
Series
Cyclone IIIr
Specifications of EP3C10M164C8N
No. Of Logic Blocks
645
Family Type
Cyclone III
No. Of I/o's
106
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Family Name
Cyclone III
Number Of Logic Blocks/elements
10320
# I/os (max)
106
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
10320
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
164
Package Type
MBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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5–30
Table 5–9. Dynamic Phase Shifting Control Signals
Cyclone III Device Handbook, Volume 1
PHASECOUNTERSELECT[2:0]
PHASEUPDOWN
PHASESTEP
SCANCLK
PHASEDONE
Signal Name
Table 5–8
PLLs.
Table 5–8. PLL Counter Settings
To bypass any of the PLL counters, set the bypass bit to 1. The values on the other bits
are then ignored.
Dynamic Phase Shifting
The dynamic phase shifting feature allows the output phase of individual PLL
outputs to be dynamically adjusted relative to each other and the reference clock
without sending serial data through the scan chain of the corresponding PLL. This
feature simplifies the interface and allows you to quickly adjust t
changing output clock phase shift in real time. This is achieved by incrementing or
decrementing the VCO phase-tap selection to a given C counter or to the M counter.
The phase is shifted by 1/8 the VCO frequency at a time. The output clocks are active
during this phase reconfiguration process.
Table 5–9
Note to
(1) Bypass bit.
X
X
Table
X
X
lists the settings for bypassing the counters in Cyclone III device family
lists the control signals that are used for dynamic phase shifting.
PLL Scan Chain Bits [0..8] Settings
5–8:
Counter Select. Three bits decoded to select
either the M or one of the C counters for
phase adjustment. One address map to select
all C counters. This signal is registered in the
PLL on the rising edge of SCANCLK.
Selects dynamic phase shift direction; 1= UP,
0 = DOWN. Signal is registered in the PLL on
the rising edge of SCANCLK.
Logic high enables dynamic phase shifting.
Free running clock from core used in
combination with PHASESTEP to enable or
disable dynamic phase shifting. Shared with
SCANCLK for dynamic reconfiguration.
When asserted, it indicates to core logic that
the phase adjustment is complete and PLL is
ready to act on a possible second adjustment
pulse. Asserts based on internal PLL timing.
Deasserts on rising edge of SCANCLK.
X
X
X
X
LSB
X
X
Description
X
X
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
X
X
X
X
1
0
MSB
(1)
(1)
Logic array or I/O
pins
Logic array or I/O
pins
Logic array or I/O
pins
GCLK or I/O pins
PLL reconfiguration
circuit
PLL counter bypassed
PLL counter not bypassed
© December 2009 Altera Corporation
Source
Description
CO
delays by
PLL Reconfiguration
PLL
reconfiguration
circuit
PLL
reconfiguration
circuit
PLL
reconfiguration
circuit
PLL
reconfiguration
circuit
Logic array or
I/O pins
Destination
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