EP3C10M164C8N Altera, EP3C10M164C8N Datasheet - Page 71
EP3C10M164C8N
Manufacturer Part Number
EP3C10M164C8N
Description
IC CYCLONE III FPGA 402MHZ BGA-164
Manufacturer
Altera
Series
Cyclone IIIr
Specifications of EP3C10M164C8N
No. Of Logic Blocks
645
Family Type
Cyclone III
No. Of I/o's
106
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Family Name
Cyclone III
Number Of Logic Blocks/elements
10320
# I/os (max)
106
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
10320
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
164
Package Type
MBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 71 of 350
- Download datasheet (8Mb)
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Clock Networks
GCLK Network Power Down
© December 2009
f
Altera Corporation
The inputs to the five clock control blocks on each side must be chosen from among
the following clock sources:
■
■
■
■
From the clock sources listed above, only two clock input pins, two PLL clock
outputs, one DPCLK or CDPCLK pin, and one source from internal logic can drive into
any given clock control block, as shown in
Out of these five inputs to any clock control block, the two clock input pins and two
PLL outputs are dynamically selected to feed a GCLK. The clock control block
supports static selection of the signal from internal logic.
Figure 5–3
the Cyclone III device family periphery.
Figure 5–3. Clock Control Blocks on Each Side of the Cyclone III Device Family
Note to
(1) The left and right sides of the device have two DPCLK pins; the top and bottom of the device have four DPCLK pins.
You can disable the Cyclone III device family GCLK (power down) by using both
static and dynamic approaches. In the static approach, configuration bits are set in the
configuration file generated by the Quartus II software, which automatically disables
unused GCLKs. The dynamic clock enable or disable feature allows internal logic to
control clock enable or disable of the GCLKs in the Cyclone III device family.
When a clock network is disabled, all the logic fed by the clock network is in an
off-state, thereby reducing the overall power consumption of the device. This function
is independent of the PLL and is applied directly on the clock network, as shown in
Figure 5–1 on page
You can set the input clock sources and the clkena signals for the GCLK
multiplexers through the Quartus II software using the ALTCLKCTRL megafunction.
For more information, refer to the
Four clock input pins
Five PLL counter outputs
Two DPCLK pins and two CDPCLK pins from both the left and right sides, and four
DPCLK pins and two CDPCLK pins from both the top and bottom
Five signals from internal logic
Figure
shows a simplified version of the five clock control blocks on each side of
5–3:
5–5.
Clock Input Pins
Internal Logic
PLL Outputs
CDPCLK
DPCLK
ALTCLKCTRL Megafunction User
2 or 4
4
5
2
5
Blocks on Each Side
Five Clock Control
of the Device
Figure 5–1 on page
Control
Clock
Block
5
Cyclone III Device Handbook, Volume 1
GCLK
5–5.
Guide.
(Note 1)
5–7
Related parts for EP3C10M164C8N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: