IS42S32800D-7TLI INTEGRATED SILICON SOLUTION (ISSI), IS42S32800D-7TLI Datasheet - Page 11

• Manufacturer Part Number: IS42S32800D-7TLI
• Description: SDRAM, IND, 8M X 32, 3V, 86TSOP2
• Manufacturer: INTEGRATED SILICON SOLUTION (ISSI)

Specifications of IS42S32800D-7TLI

• Access Time: 5.5ns
• Page Size: 256Mbit
• Memory Case Style: TSOP-2
• No. Of Pins: 86
• Operating Temperature Range: -40°C To +85°C
• Memory Type: DRAM - Synchronous
• Memory Configuration: 4 BLK (2M X 32)
• Interface Type: LVTTL
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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IS42S32800D
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
11/21/07
CLK
COMMAND
DQ0 - DQ3
CLK
ADDRESS
COMMAND
CAS# latency=2
t CK2 , DQ s
CAS# latency=3
t CK3 , DQ s
A write burst without the AutoPrecharge function may be interrupted by a subsequent Write, BankPrecharge/
PrechargeAll,or Read command before the end of the burst length.An interrupt coming from Write command can
occur on any clock cycle following the previous Write command (refer to the following figure).
Write command
(RAS#=”H”,CAS#=”L”,WE#=”L”,BS =Bank,A10 =”L”,A0-A8 =Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active row in an active
bank.The bank must be active for at least tRCD(min.)before the Write command is issued.During write bursts,
the first valid data-in element will be registered coincident with the Write command.Subsequent data elements
will be registered on each successive positive clock edge (refer to the following figure).The DQs remain with high-
impedance at the end of the burst unless another command is initiated.The burst length and burst sequence are
determined by the mode register,which is already programmed.A full-page burst will continue until terminated (at
the end of the page it will wrap to column 0 and continue).
Burst Write Operation (Burst Length =4,CAS#Latency =2,3)
The first data element and the write
are registered on the same clock edge.
READ A
Col A
Bank,
T0
T0
NOP
WRITEA
DIN A 0
Read to Precharge (CAS#Latency =2,3)
T1
T1
NOP
I
DOUT A 0
DIN A 1
T2
T2
NOP
NOP
DOUT A 0
DIN A 2
T3
T3
NOP
DOUT A 1
NOP
Bank(s )
Precharge
DOUT A 2
DIN A 3
T4
T4
NOP
DOUT A 1
Extra data is masked.
don’t care
DOUT A 2
T5
T5
DOUT A 3
NOP
NOP
t
RP
T6
T6
DOUT A 3
NOP
NOP
Activate
T7
Bank,
Row
T7
NOP
T8
T8
NOP
NOP
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