IS42S32800D-7TLI INTEGRATED SILICON SOLUTION (ISSI), IS42S32800D-7TLI Datasheet - Page 7
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IS42S32800D-7TLI
Manufacturer Part Number
IS42S32800D-7TLI
Description
SDRAM, IND, 8M X 32, 3V, 86TSOP2
Manufacturer
INTEGRATED SILICON SOLUTION (ISSI)
Datasheet
1.IS42S32800D-7TL.pdf
(62 pages)
Specifications of IS42S32800D-7TLI
Access Time
5.5ns
Page Size
256Mbit
Memory Case Style
TSOP-2
No. Of Pins
86
Operating Temperature Range
-40°C To +85°C
Memory Type
DRAM - Synchronous
Memory Configuration
4 BLK (2M X 32)
Interface Type
LVTTL
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IS42S32800D-7TLI
Manufacturer:
ISSI
Quantity:
20 000
Commands
IS42S32800D
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
11/21/07
2
1
BankPrecharge command
(RAS#=”L”,CAS#=”H”,WE#=”L”,BS =Bank,A10 =”L”)
The BankPrecharge command precharges the bank disignated by BS0,1 signal.The
precharged bank is switched from the active state to the idle state.This command can be asserted anytime after
tRAS(min.)is satisfied from the BankActivate command in the desired bank.The maximum time any bank can be
active is specified by tRAS(max.).Therefore,the precharge function must be performed in any active bank within
tRAS(max.).At the end of precharge,the precharged bank is still in the idle state and is ready to be activated again.
CLK
ADDRESS
C O M M A N D
(RAS#=”L”,CAS#=”H”,WE#=”H”,BS =Bank,A0-A11 =Row Address)
The BankActivate command activates the idle bank designated by the BS0,1 (Bank Select) signal.By latching the
row address on A0 to A11 at the time of this command,the selected row access is initiated.The read or write
operation in the same bank can occur after a time delay of tRCD(min.)from the time of bank activation.A
subsequent BankActivate command to a different row in the same bank can only be issued after the previous
active row has been precharged (refer to the following figure).The minimum time interval between successive
BankActivate commands to the same bank is defined by tRC(min.).The SDRAM has four internal banks on the
same chip and shares part of the internal circuitry to reduce chip area;therefore it restricts the back-to-back
activation of the four banks.tRRD(min.)specifies the minimum time required between activating different banks.
After this command is used,the Write command and the Block Write command perform the no mask write
operation.
BankActivate
:"H" or "L"
Row Addr.
Activate
Bank A
Bank A
T0
RAS# - CAS# delay (
T1
NOP
Bank
T2
NOP
t
RCD
)
AutoPrecharge
Col Addr.
T3
R/W A with
Bank A
RAS# Cycle time (
..............
..............
..............
t
RC
)
Auto Precharge
Row Addr.
Tn+3
Begin
Activate
Bank B
Bank B
RAS#- RAS# delay time (
Tn+4
NOP
Tn+5
NOP
t
RRD
)
Row Addr.
Activate
Bank A
Bank A
Tn+6
7