IS43DR16160A-37CBL INTEGRATED SILICON SOLUTION (ISSI), IS43DR16160A-37CBL Datasheet

Page 1

IS43/46DR83200A IS43/46DR16160A 32Mx8, 16Mx16 DDR2 DRAM FEATURES • 1.8V ±0.1V 1.8V ±0.1V dd ddq • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 internal banks for concurrent operation • Programmable CAS latency (CL and 6 supported • Posted CAS and programmable additive latency (AL and 5 supported • WRITE latency = READ latency - 1 tCK • Programmable burst lengths • Adjustable data-output drive strength, full and reduced strength options • On-die termination (ODT) OPTIONS  ...

Page 2

IS43/46DR83200A, IS43/46DR16160A GENERAL DESCRIPTION Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the active command are used to select the bank and row to be accessed (BA0-BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location (A0-A8 for x16) and (A0-A9 for x8) for the burst access and to determine if the auto precharge A10 command issued. Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. FUNCTIONAL BLOCK DIAGRAM Notes: 1. An:n = no. of address pins - 1 2. DQm no. of data pins - 1 3. For x8 devices: DMa - DMb = ...

Page 3

IS43/46DR83200A, IS43/46DR16160A PIN DESCRIPTION TABLE Symbol  Type  Function  Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. CK, CK Input Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE LOW deactivates, internal clock signals and device input buffers and output drivers. Taking CKE LOW provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. After VREF has become CKE Input stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained HIGH throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self refresh. Chip Select: All commands are masked when CS is registered HIGH. CS provides for Input CS external Rank selection on systems with multiple Ranks considered part of the command code. On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS, DM ODT Input signals. The ODT pin will be ignored if the EMR(1) is programmed to disable ODT. RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being ...

Page 4

IS43/46DR83200A, IS43/46DR16160A Symbol  Type  Function  DQ0-7 x8 Input/ Data Input/Output: Bi-directional data bus. DQ0-15 x16 Output Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. The data strobes DQS(n) may be used in single ended mode or paired with optional complementary signals DQS(n) to provide differential pair signaling to the system during both reads and writes. A control bit at EMR(1)[A10] DQS, (DQS) enables or disables all complementary data strobe signals. RDQS, (RDQS Input/ DQS corresponds to the data on DQ0-DQ7 Output UDQS, (UDQS), RDQS corresponds to the Read data on DQ0-DQ7, and is enabled by EMRS LDQS, (LDQS) x16 command to EMR(1) [A11]. x16 LDQS corresponds to the data on DQ0-DQ7 UDQS corresponds to the data on DQ8-DQ15 NC No Connect: No internal electrical connection is present. VDDQ Supply DQ Power Supply: 1.8 V +/- 0.1 V VSSQ Supply DQ Ground ...

Page 5

IS43/46DR83200A, IS43/46DR16160A PIN CONFIGURATION PACKAGE CODE BALL FBGA (Top View) (8. 10.5 mm Body, 0.8 mm Ball Pitch Pin name Function A0 to A12 Address inputs BA0, BA1 Bank select DQ0 to DQ7 Data input/output DQS, /DQS Differential data strobe /CS Chip select /RAS, /CAS, /WE Command input CKE Clock enable CK, /CK Differential clock input DM Write data mask RDQS, /RDQS Differential Redundant Data Strobe Integrated Silicon ...

Page 6

IS43/46DR83200A, IS43/46DR16160A PIN CONFIGURATION PACKAGE CODE BALL FBGA (Top View) (8. 12.50 mm Body, 0.8 mm Ball Pitch Pin name Function A0 to A12 Address inputs BA0, BA1 Bank select DQ0 to DQ15 Data input/output LDQS, UDQS Differential data strobe /LDQS, /UDQS /CS Chip select /RAS, /CAS, /WE Command input CKE Clock enable CK, /CK Differential clock input LDM to UDM ...

Page 7

IS43/46DR83200A, IS43/46DR16160A ELECTRICAL SPECIFICATIONS Absolute Maximum DC Ratings Symbol  Parameter  V Voltage on VDD pin relative to Vss dd V Voltage on VDDQ pin relative to Vss ddq V Voltage on VDDL pin relative to Vss ddl Voltage on any pin relative to Vss in out T Storage Temperature stg Notes: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6 x VDDQ. When VDD and VDDQ and VDDL are less than 500 mV, Vref may be equal to or less than 300 mV. 4. Voltage on any input or I/O may not exceed voltage on VDDQ. AC & DC Recommended Operating Conditions ...

Page 8

IS43/46DR83200A, IS43/46DR16160A Operating Temperature Condition Symbol Parameter TOPER Commercial Temperature Industrial Temperature, Automotive Temperature (A1) Automotive Temperature (A2) Notes Operating case temperature at center of package Operating ambient temperature immediately above package center Both temperature specifications must be met. Thermal Resistance Package Substrate (Airflow = 0m/s) 60-ball BGA 4-layer 84-ball BGA 4-layer ODT DC Electrical Characteristics PARAMETER/CONDITION  R effective impedance value for EMR(1)[A6,A2]=0,1; 75 Ω effective impedance value for EMR(1)[A6,A2]=1,0; 150 Ω effective impedance value for EMR(1)[A6,A2]=1,1; 50 Ω ...

Page 9

IS43/46DR83200A, IS43/46DR16160A Input DC logic level Symbol  Parameter VIH(dc) dc input logic HIGH VIL(dc) dc input logic LOW Input AC logic level Symbol Parameter VIH (ac) ac input logic HIGH VIL (ac) ac input logic LOW Notes: 1. Refer to Overshoot/undershoot specifications for Vpeak value: maximum peak amplitude allowed for overshoot and undershoot. AC Input Test Conditions Symbol Condition VREF Input reference voltage VSWING(MAX) Input signal maximum peak to peak swing SLEW Input signal minimum slew rate Notes: 1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test. 2. The input signal minimum slew rate maintained over the range from VREF to VIH(ac) min for rising edges and the range from VREF to VIL(ac) max for falling edges as shown in the below figure timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. AC input test signal waveform V SWING(MAX) ...

Page 10

IS43/46DR83200A, IS43/46DR16160A Differential input AC Logic Level Symbol Parameter VID (ac) ac differential input voltage VIX (ac) ac differential crosspoint voltage Notes: 1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS and VCP is the complementary input signal (such DQS). The minimum value is equal to VIH(AC) - VIL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ. VIX(AC) indicates the voltage at which differential input signals must cross. 3. Refer to Overshoot/undershoot specifications for Vpeak value: maximum peak amplitude allowed for overshoot and undershoot. Differential signal levels Differential AC Output Parameters Symbol Parameter VOX (ac) ac differential crosspoint voltage Note: 1. The typical value of VOX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ. VOX(AC) indicates the voltage at which differential output signals must cross. 10 Min. Max. 0.5 VDDQ 0.5 x VDDQ - 0.175 0.5 x VDDQ + 0.175 V ...

Page 11

IS43/46DR83200A, IS43/46DR16160A OVERShOOT/UNDERShOOT SPECIFICATION AC overshoot/undershoot specification for Address and Control pins Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area Maximum overshoot area above VDD (see figure below) Maximum undershoot area below VSS (see figure below) Maximum Amplitude V DD Volts V SS (V) Maximum Amplitude AC overshoot and undershoot definition for address and control pins AC overshoot/undershoot specification for Clock, Data, Strobe, and Mask pins: DQ, (U/L/R) DQS, (U/L/R) DQS, DM, CK, CK Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area Maximum overshoot area above VDDQ (See Figure below) Maximum undershoot area below VSSQ (See Figure below) Maximum Amplitude V DDQ Volts V SSQ (V) Maximum Amplitude AC overshoot and undershoot definition for clock, data, strobe, and mask pins Integrated Silicon ...

Page 12

IS43/46DR83200A, IS43/46DR16160A Output Buffer Characteristics Output AC Test Conditions Symbol Parameter VOTR Output Timing Measurement Reference Level Output DC Current Drive Symbol Parameter IOH(dc) Output Minimum Source DC Current IOL(dc) Output Minimum Sink DC Current Notes: 1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 Ω for values of VOUT between VDDQ and VDDQ - 280 mV. 2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 Ω for values of VOUT between 0 V and 280 mV. 3. The dc value of VREF applied to the receiving device is set to VTT 4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point (see Section 3.3 of JESD8-15A) along a 21 Ω load line to define a convenient driver cur- rent for measurement. OCD Default Characteristics Description Parameter Output impedance Output impedance step size for OCD calibration Pull-up and pull-down mismatch Output slew rate Sout Notes: 1. Absolute Specifications (TOPER; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V). DRAM I/O specifications for timing, voltage, and slew rate are no ...

Page 13

IS43/46DR83200A, IS43/46DR16160A IDD Specifications & Test Conditions  Conditions Symbol     IDD0 Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING IDD1 Operating one bank active-read-precharge current; IOUT = 0mA CL(IDD tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current; All banks idle; IDD2P tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING IDD2Q Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; IDD2N tCK = tCK(IDD); CKE is HIGH HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; IDD3P tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; ...

Page 14

IS43/46DR83200A, IS43/46DR16160A IDD Specifications & Test Conditions (continued) Conditions Symbol     IDD4R Operating burst read current; All banks open, Continuous burst reads, IOUT = 0 mA CL(IDD tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W IDD5B Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; IDD6 CK and CKE ≤ 0.2 V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING IDD7 Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA CL(IDD tRCD(IDD tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1 x tCK(IDD); CKE is HIGH HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Notes: 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition ...

Page 15

IS43/46DR83200A, IS43/46DR16160A IDD testing parameters Speed DDR2-800 Bin(CL-tRCD-tRP) 6-6-6 CL(IDD) 6 tRCD(IDD) 15 tRC(IDD) 60 tRRD(IDD) 7.5 tCK(IDD) 2.5 tRASmin(IDD) 45 tRASmax(IDD) 70 tRP(IDD) 15 tRFC(IDD) 75 Input/Output Capacitance: Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, DQS Integrated Silicon Solution, Inc. ...

Page 16

IS43/46DR83200A, IS43/46DR16160A Electrical Characteristics & AC Timing Specifications Refresh parameters (TOPER; VDDQ = 1.8 V +/- 0.1 V; VDD = 1.8 V +/- 0.1 V) Parameter Refresh to active/Refresh command time Average periodic refresh interval Notes refresh timing is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 2. Specified for Industrial and Automotive grade only; not applicable for Commercial grade Specified for Automotive grade (A2) only; not applicable for any other grade. T Key Timing Parameters by Speed Grade -25E Speed bin (JEDEC) DDR2-800E CL-tRCD-tRP 6-6-6 tRCD 15 tRP 15 tRC 60 tRAS 45 tCK(avg)@CL=3 5 tCK(avg)@CL=4 3.75 tCK(avg)@CL=5 3 tCK(avg)@CL=6 2.5 16 Symbol tRFC -40 ...

Page 17

IS43/46DR83200A, IS43/46DR16160A Timing Parameters by Speed Grade (DDR2-400 and DDR2-533) (For information related to the entries in this table, refer to both the Guidelines and the Specific Notes following this Table.) Parameter Clock cycle time, CL=x CK HIGH pulse width CK LOW pulse width DQS latching rising transitions to associated clock edges DQS falling edge to CK setup time DQS falling edge hold time from CK DQS input HIGH pulse width DQS input LOW pulse width Write preamble Write postamble Address and control input setup time Address and control input hold time Control & Address input pulse width for each input DQ and DM input setup time (differential strobe) DQ and DM input hold time (differential strobe) DQ and DM input setup time (single-ended strobe) DQ and DM input hold time (single-ended strobe) DQ and DM input pulse width for each input DQ output access time from CK/CK DQS output access time from CK/ CK Data-out high-impedance time from CK/ CK DQS(DQS) low-impedance time from CK low-impedance time from CK/ CK DQS-DQ skew for DQS and associated DQ signals CK half pulse width DQ hold skew factor DQ/DQS output hold time from DQS Read preamble Read postamble Integrated Silicon Solution, Inc. — ...

Page 18

IS43/46DR83200A, IS43/46DR16160A Timing Parameters by Speed Grade (DDR2-400 and DDR2-533) cont'd (For information related to the entries in this table, refer to both the Guidelines and the Specific Notes following this Table.) Parameter Active to active command period CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay tRTP CKE minimum pulse width (HIGH and LOW pulse width) Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any non- read command Exit active power down to read command tXARD Exit active power down to read command (slow exit, lower power) ODT turn-on delay ODT turn-on ODT turn-on (Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT power down exit latency Mode register set command cycle time MRS command to ODT update delay OCD drive mode output delay Minimum time clocks remains ON after CKE asynchronously drops LOW 18 DDR2-400 Symbol Min. ...

Page 19

IS43/46DR83200A, IS43/46DR16160A Timing Parameters by Speed Grade (DDR2-667 and DDR2-800) (For information related to the entries in this table, refer to both the Guidelines and the Specific Notes following this Table.) Parameter Average clock period Average clock HIGH pulse width Average clock LOW pulse width DQS latching rising transitions to associated clock edges DQS falling edge to CK setup time DQS falling edge hold time from CK DQS input HIGH pulse width DQS input LOW pulse width Write preamble Write postamble Address and control input setup time Address and control input hold time Control & Address input pulse width for each input DQ and DM input setup time DQ and DM input hold time DQ and DM input pulse width for each input DQ output access time from CK/CK DQS output access time from CK/CK Data-out high-impedance time from CK/CK DQS/DQS low-impedance time from CK/CK tLZ(DQS) DQ low-impedance time from CK/CK DQS-DQ skew for DQS and associated DQ signals CK half pulse width DQ hold skew factor DQ/DQS output hold time from DQS Read preamble Read postamble Integrated Silicon Solution, Inc. ...

Page 20

IS43/46DR83200A, IS43/46DR16160A Timing parameters by speed grade (DDR2-667 and DDR2-800) cont'd (For information related to the entries in this table, refer to both the Guidelines and the Specific Notes following this Table.) Parameter Activate to activate command period CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay CKE minimum pulse width (HIGH and LOW pulse width) Exit self refresh to a non-read command tXSNR Exit self refresh to a read command Exit precharge power down to any command Exit active power down to read command Exit active power down to read command (slow exit, lower power) ODT turn-on delay ODT turn-on ODT turn-on (Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT Power Down Exit Latency Mode register set command cycle time OCD drive mode output delay Minimum time clocks remains ON after CKE asynchronously drops LOW 20 DDR2-667 Symbol Min. ...

Page 21

IS43/46DR83200A, IS43/46DR16160A Guidelines for AC Parameters 1. DDR2 SDRAM AC Timing Reference Load Figure "AC Timing Reference Load" represents the timing reference load used in defining the relevant timing parameters of the part not intended to be either a precise representation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). VDDQ DQ DQS Output DUT DQS RDQS Timing RDQS reference point Figure - AC Timing Reference Load The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal. 2. Slew Rate Measurement Levels a) Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS = - 500 mV and DQS - DQS = + 500 mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device. b) Input slew rate for single ended signals is measured from Vref(dc) to VIH(ac),min for rising edges and from Vref(dc) to VIL(ac),max for falling edges. For differential signals (e. CK) slew rate for rising edges is measured from 250 500 mV (+ 250 500 mV for falling edges). c) VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential strobe. 3. DDR2 SDRAM output slew rate test load ...

Page 22

IS43/46DR83200A, IS43/46DR16160A t DQSH DQS DQS/ DQS DQS t WPRE V (ac (ac DMin Data Input (Write) Timing CK/CK CK DQS DQS/DQS DQS t RPRE DQ Data Output (Read) Timing 5. AC timings are for linear signal transitions. See Specific Notes on derating for other signal transitions. 6. All voltages are referenced to VSS. 7. These parameters guarantee device behavior, but they are not necessarily tested on each device They may be guaranteed by device design or tester correlation. 8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply ...

Page 23

IS43/46DR83200A, IS43/46DR16160A 7. Timings are specified with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1 V/ns in single ended mode. See Specific Notes on derating for other slew rate values. 8. Data setup and hold time derating (t DtDS, DtDH derating values for DDR2-400, DDR2-553 (All units in ‘ps’; the note applies to the entire table) 4.0 V/ns 3.0 V/ns DtDS DtDH DtDS DtDH DtDS DtDH DtDS DtDH DtDS DtDH DtDS DtDH DtDS DtDH DtDS DtDH DtDS DtDH DQ 2.0 125 45 125 45 Slew 1 rate ...

Page 24

IS43/46DR83200A, IS43/46DR16160A DtDS1, DtDH1 derating values for DDR2-400, DDR2-533 (All units in ‘ps’; the note applies to the entire table) 2.0 V/ns 1.5 V/ns DtDS1 DtDH1 DtDS1 DtDH1 DtDS1 DtDH DtDS1 DtDH1 DtDS1 DtDH1 DtDS1 DtDH1 DtDS1 DtDH1 DtDS1 DtDH1 DtDS1 DtDH1 DQ 2.0 188 167 145 125 Slew 1.5 146 167 125 125 rate 1.0 63 125 42 ...

Page 25

IS43/46DR83200A, IS43/46DR16160A 9. Input Setup and Hold Time Derating (tIS, tIH) tIS, tIH Derating Values for DDR2-400, DDR2-533 DtIS 4.0 187 3.5 179 3 167 2.5 150 2.0 125 1.5 83 1.0 0 0.9 -11 Command/ 0.8 -25 Address Slew rate 0.7 -43 (V/ns) 0.6 -67 0.5 -110 0.4 -175 ...

Page 26

IS43/46DR83200A, IS43/46DR16160A DtIS and DtIH Derating Values for DDR2-667, DDR2-800 2.0 V/ns DtIS 4 150 3.5 143 3 133 2.5 120 2 100 1 Command/ 0.9 -5 Address 0.8 -13 0.7 -22 Slew rate 0.6 -34 (V/ns) 0.5 -60 0.4 -100 0.3 -168 0.25 -200 0.2 ...

Page 27

IS43/46DR83200A, IS43/46DR16160A 10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 11. MIN ( tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). For example, tCL and tCH are = 50% of the period, less the half period jitter ( tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk ( tJIT(crosstalk)) into the clock traces. 12. tQH = tHP – tQHS, where minimum half clock period for any given cycle and is defined by clock HIGH or clock LOW (tCH, tCL). tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one transition followed by the worst case pull- the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in any given cycle. 14. tDAL = WR + RU{ tRP[ns] / tCK[ns] }, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For DDR533 at tCK = 3.75ns with WR programmed to 4 clocks. tDAL = 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 15. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In case of clock frequency change during precharge power-down, a specific procedure is required as described in section 3.13. 16. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns. For DDR2-667/800, tAOND is 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges. 17. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD, which is interpreted differently per speed bin. For ...

Page 28

IS43/46DR83200A, IS43/46DR16160A 20. Input waveform timing tDS with differential data strobe enabled is referenced from the input signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(dc)max and Vih(dc)min. 21. Input waveform timing tDH with differential data strobe enabled is referenced from the differential data strobe crosspoint to the input signal crossing at the VIH(dc) level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL(dc) level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(dc)max and Vih(dc)min. 22. Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling signal applied to the device under test. 23. Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the device under test. 24. tWTR is at lease two clocks (2 x tCK nCK) independent of operation frequency. 25. Input waveform timing with single-ended data strobe enabled, is referenced from the input signal crossing at the VIH(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be monotonic between Vil(dc)max and Vih(dc)min. 26. Input waveform timing with single-ended data strobe enabled, is referenced from the input signal crossing at the VIH(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be monotonic between Vil(dc)max and Vih(dc)min. 27. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. 28. If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 29. ...

Page 29

IS43/46DR83200A, IS43/46DR16160A 33. tDAL [nCK [nCK] + tnRP [nCK {tRP [ps] / tCK(avg) [ps] }, where WR is the value programmed in the mode register set. 34. New units, ‘tCK(avg)’ and ‘nCK’, are introduced in DDR2-667 and DDR2-800. Unit ‘tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ‘nCK’ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, ‘tCK’ is used for both concepts. ex) tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm+2, even if (Tm tCK(avg) + tERR(2per),min. 35. Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec parameters' and these parameters apply to DDR2-667 and DDR2-800 only. The jitter specified is a random jitter meeting a Gaussian distribution. Parameter Clock period jitter Clock period jitter during DLL locking period Cycle to cycle clock period jitter Cycle to cycle clock period jitter during DLL locking period Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across n cycles ... 10, inclusive Cumulative error across n cycles ... 50, inclusive Duty cycle jitter Integrated Silicon Solution, Inc. — www.issi.com Rev.  A ...

Page 30

IS43/46DR83200A, IS43/46DR16160A 36. These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. (Min and max of SPEC values are to be used for calculations in the table below.) Parameter Symbol Absolute clock period tCK(abs) Absolute clock HIGH tCH(abs) pulse width Absolute clock LOW tCL(abs) pulse width Example: For DDR2-667, tCH(abs),min = ( 0.48 x 3000 125 ps = 1315 ps 37. tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = Min ( tCH(abs), tCL(abs) ), where, tCH(abs) is the minimum of the actual instantaneous clock HIGH time; tCL(abs) is the minimum of the actual instantaneous clock LOW time; 38. tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull- the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation of the output drivers 39. tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples the system provides tHP of 1315 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975 ps minimum the system provides tHP of 1420 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080 ps minimum. ...

Page 31

IS43/46DR83200A, IS43/46DR16160A 41. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(per),min = - 72 ps and tJIT(per),max = + 93 ps, then tRPRE,min(derated) = tRPRE,min + tJIT(per),min = 0.9 x tCK(avg 2178 ps and tRPRE,max(derated) = tRPRE,max + tJIT(per),max = 1.1 x tCK(avg 2843 ps. (Caution on the min/max usage!) 42. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(duty) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(duty),min = - 72 ps and tJIT(duty),max = + 93 ps, then tRPST,min(derated) = tRPST,min + tJIT(duty),min = 0.4 x tCK(avg 928 ps and tRPST,max(derated) = tRPST,max + tJIT(duty),max = 0.6 x tCK(avg 1592 ps. (Caution on the min/max usage!) 43. When the device is operated with input clock jitter, this parameter needs to be derated by { -tJIT(duty),max - tERR(6-10per),max } and { - tJIT(duty),min - tERR(6-10per),min } of the actual input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per),min = - 272 ps, tERR(6-10per),max = + 293 ps, tJIT(duty),min = - 106 ps and tJIT(duty),max = + 94 ps, then tAOF,min(derated) = tAOF,min + { - tJIT(duty), max - tERR(6-10per),max } = - 450 293 ps 837 ps and tAOF,max(derated) = tAOF,max + { - tJIT(duty),min - tERR(6-10per),min } = 1050 106 ps + 272 1428 ps. (Caution on the min/max usage!) 44. For tAOFD of DDR2-400/533, the 1/2 clock of tCK in the 2.5 x tCK assumes a tCH, input clock HIGH pulse width of 0.5 relative to tCK. tAOF,min and tAOF,max should each be derated by the same amount as the actual amount of tCH offset present at the DRAM input with respect to 0.5. For example input clock has a worst case tCH of 0.45, the tAOF,min should be derated by subtracting 0.05 x tCK from it, whereas if an input clock has a worst case tCH of 0.55, the tAOF,max should be derated by adding 0.05 x tCK to it. Therefore, we have; tAOF,min(derated) = tAC,min - [0.5 - Min(0.5, tCH,min)] x tCK tAOF,max(derated) = tAC,max + 0.6 + [Max(0.5, tCH,max) - 0.5] x tCK or tAOF,min(derated) = Min(tAC,min, tAC,min - [0.5 - tCH,min] x tCK) tAOF,max(derated) = 0.6 + Max(tAC,max, tAC,max + [tCH,max - 0.5] x tCK) where tCH,min and tCH,max are the minimum and maximum of tCH actually measured at the DRAM input balls. 45. For tAOFD of DDR2-667/800, the 1/2 clock of nCK in the 2.5 x nCK assumes a tCH(avg), average input clock HIGH pulse width of 0.5 relative to tCK(avg). tAOF,min and tAOF,max should each be derated by the same amount as the actual amount of tCH(avg) offset present at the DRAM input with respect to 0.5. For example input clock has a worst case tCH(avg) of 0.48, the tAOF,min should be derated by subtracting 0.02 x tCK(avg) from it, whereas ...

Page 32

IS43/46DR83200A, IS43/46DR16160A FUNCTIONAL DESCRIPTION Power-up and Initialization DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. For DDR2 SDRAMs, both bits BA0 and BA1 must be decoded for Mode/ Extended Mode Register Set (MRS/EMRS) commands. Users must initialize all four Mode Registers. The registers may be initialized in any order. Power-up and Initialization Sequence The following sequence is required for Power-up and Initialization. a) Either one of the following sequence is required for Power-up. a1) While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT LOW state (all other inputs may be undefined.) The VDD voltage ramp time must be no greater than 200 ms from when VDD ramps from 300 mV to VDD min; and during the VDD voltage ramp, |VDD-VDDQ| ≤ 0.3 volts. Once the ramping of the supply voltages is complete (when VDDQ crosses VDDQ min), the supply voltage specifications provided in "Recommended DC operating conditions" (SSTL_1.8), prevail. - VDD, VDDL and VDDQ are driven from a single power converter output, AND - VTT is limited to 0.95V max, AND - VREF tracks VDDQ/2, VREF must be within +/- 300mV with respect to VDDQ/2 during supply ramp time. - VDDQ ≥ VREF must be met at all times. a2) While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT LOW state, all other inputs may be undefined, voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid DRAM latch-up. During the ramping of the supply voltages, VDD ≥ VDDL ≥ VDDQ must be maintained and is applicable to both AC and DC levels until the ramping of the supply voltages is complete, which is when VDDQ crosses VDDQ min. Once the ramping of the supply voltages is complete, the supply voltage specifications provided in "Recommended DC operating conditions" (SSTL_1.8), prevail. - Apply VDD/VDDL before or at the same time as VDDQ. - VDD/VDDL voltage ramp time must be no greater than 200ms from when VDD ramps from 300mV to VDD min - Apply VDDQ before or at the same time as VTT. - The VDDQ voltage ramp time from when VDD min is achieved on VDD to when VDDQ min is achieved on VDDQ must be no greater than 500ms. (Note: While VDD is ramping, current may be supplied from VDD through the DRAM to VDDQ.) - VREF must track VDDQ/2, VREF must be within +/- 300mv with respect to VDDQ/2 during supply ramp time. - VDDQ ≥ VREF must be met at all times. - Apply VTT. - The VTT voltage ramp time from when VDDQ min is achieved on VDDQ to when VTT min is achieved on VTT must be no greater than 500ms. b) Start clock and maintain stable condition. c) For the minimum of 200ms after stable power (VDD, VDDL, VDDQ, VREF and VTT are between their minimum and maximum values as stated in "Recommended DC operating conditions" (SSTL_1.8)) and stable clock (CK, CK), then ...

Page 33

IS43/46DR83200A, IS43/46DR16160A Power-up and Initialization Sequence (cont'd) f) Issue an EMRS command to EMR(3). g) Issue EMRS to enable DLL. h) Issue a Mode Register Set command for DLL reset. i) Issue a precharge all command. j) Issue 2 or more auto-refresh commands. k) Issue a MRS command with LOW initialize device operation. (i.e. to program operating parameters without resetting the DLL least 200 clocks after step h, execute OCD Calibration (Off Chip Driver impedance adjustment). If OCD calibration is not used, EMRS to EMR(1) to set OCD Calibration Default (A9=A8=A7=HIGH) followed by EMRS to EMR(1) to exit OCD Calibration Mode (A9=A8=A7=LOW) must be issued with other operating parameters of EMR(1). m) The DDR2 SDRAM is now ready for normal operation. tCH tCL CK /CK tIS CKE ODT PRE Command NOP EMRS ALL tRP 400ns DLL ENABLE Initialization Sequence after Power-Up Programming the Mode and Extended Mode Registers For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time (WR) are user defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, driver impedance, additive CAS latency, ODT (On Die Termination), single-ended strobe, and OCD (off chip driver impedance adjustment) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register or Extended Mode Registers can be altered by re- executing the MRS or EMRS Commands. Even if the user chooses to modify only a subset of the MR, or EMR(1), ...

Page 34

IS43/46DR83200A, IS43/46DR16160A Mode Register (MR) The mode register stores the data for controlling the various operating modes of the DDR2 SDRAM. It controls CAS latency, burst length, burst sequence, test mode, DLL reset, and Write Recovery time (WR) to make DDR2 SDRAM useful for various applications. The default value of the mode register is not defined, therefore the mode register must be programmed during initialization for proper operation. The mode register is written by asserting LOW on CS, RAS, CAS, WE, BA0 and BA1, while controlling the state of address pins A0 - A12. The DDR2 SDRAM should be in all bank precharge state with CKE already HIGH prior to writing into the mode register. The mode register set command cycle time (tMRD) is required to complete the write operation to the mode register. The mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. The mode register is divided into various fields depending on functionality. Burst length is defined with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with DDR SDRAM. Burst address sequence type is defined by A3, CAS latency is defined A6. The DDR2 does not support half clock latency mode mode bit and must be set to LOW for normal MRS operation used for DLL reset. Write recovery time WR is defined A11. Refer to the table for specific codes. 34 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 04/08/2011 ...

Page 35

IS43/46DR83200A, IS43/46DR16160A DDR2 SDRAM Mode Register Set (MRS) A12 Address Mode Field Register BA1 0 0 BA0 A11 A12 PD A11 A10 DLL CAS A5 Latency Burst A1 Length A0 Notes: 1. For DDR2-400/533, WR (write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer (WR[cycles] = RU{ tWR[ns] / tCK[ns] }, where RU stands for round up). For DDR2-667/800, WR min is determined by tCK(avg) max and WR max is determined by tCK(avg) min. WR[cycles] = ...

Page 36

IS43/46DR83200A, IS43/46DR16160A Burst mode operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst length. DDR2 SDRAM supports 4 bit burst and 8 bit burst modes only. For 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst type, either sequential or interleaved, is programmable and defined by MR[A3], which is similar to the DDR SDRAM operation. Seamless burst read or write operations are supported. Unlike DDR devices, interruption of a burst read or write cycle during mode operation is prohibited. However in case mode, interruption of a burst read or write operation is limited to two cases, reads interrupted by a read, or writes interrupted by a write. Therefore the Burst Stop command is not supported on DDR2 SDRAM devices. Burst Length and Sequence Burst Length Starting Address (A1, A0 Burst Length Starting Address (A2, A1, A0) Sequential Addressing (decimal Sequential Addressing (decimal ...

Page 37

IS43/46DR83200A, IS43/46DR16160A Extended Mode Registers (EMR) Extended Mode Register 1 (EMR1) The EMR(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency, ODT, DQS disable, OCD program, RDQS enable. The default value of the EMR(1) is not defined, therefore the extended mode register must be programmed during initialization for proper operation. The EMR(1) is written by asserting LOW on CS, RAS, CAS, WE, HIGH on BA0 and LOW on BA1, while controlling the states of address pins A0 - A12. The DDR2 SDRAM should be in all bank precharge with CKE already HIGH prior to writing into the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register. Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. DLL enable/disable The DLL must be enabled for normal operation. DLL enable is required during power-up and initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 04/08/2011 37 ...

Page 38

IS43/46DR83200A, IS43/46DR16160A A12 0 Address Mode Field Register 1 BA1 0 BA0 1 A11 0 A12 Qff 1 A10 *1 A11 RDQS 0 1 A10 /DQS OCD A8 Program Rtt A5 ...

Page 39

IS43/46DR83200A, IS43/46DR16160A Extended Mode Register 2 (EMR2) The Extended Mode Register 2 controls refresh related features. The default value of the EMR(2) is not defined, therefore the mode register must be programmed during initialization for proper operation. The EMR(2) is written by asserting LOW on CS, RAS, CAS, WE, HIGH on BA1 and LOW on BA0, while controlling the states of address pins A0 - A12. The DDR2 SDRAM should be in all bank precharge state with CKE already HIGH prior to writing into the EMR(2). The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the EMR(2). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. Address Mode Field Register BA1 1 BA0 A12 *1 0 A11 *1 0 A10 * SRF * ...

Page 40

IS43/46DR83200A, IS43/46DR16160A DDR2 SDRAM Extended Mode Register 3 (EMR3) No function is defined in Extended Mode Register (3). The default value of the EMR(3) is not defined, therefore the EMR(3) must be programmed during initialization for proper operation. All bits in EMR(3) except BA0 and BA1 are reserved for future use and must be set to 0 when programming this mode register. Address Field BA1 BA0 A12 A11 Mode Register A10 Integrated Silicon Solution, Inc. — www.issi.com ...

Page 41

IS43/46DR83200A, IS43/46DR16160A TRUTh TABLES Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the speechified initialization sequence before normal operation can continue. Command Truth Table Function CKE Previous Current Cycle Cycle (Extended) Mode H H Register Set (Load Mode) Refresh (REF Self Refresh Entry H L Self Refresh Exit L H Single Bank H H Precharge Precharge all Banks H H Bank Activate H H Write H ...

Page 42

IS43/46DR83200A, IS43/46DR16160A Clock Enable (CKE) Truth Table Current  CKE State 2 Previous Cycle   Current Cycle 1 (N-1) Power Down L L Self Refresh L L Bank(s) H Active All Banks H Idle H H Notes: 1. CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge. 2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge N. 3. COMMAND (N) is the command registered at clock edge N, and ACTION ( result of COMMAND (N). 4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. 6. Self Refresh mode can only be entered from the All Banks Idle state. ...

Page 43

IS43/46DR83200A, IS43/46DR16160A DESELECT The DESELECT function (CS HIGH) prevents new commands from being executed by the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in progress are not affected. DESELECT is also referred to as COMMAND INHIBIT. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to instruct the selected DDR2 SDRAM to perform a NOP (CS is LOW; RAS, CAS, and WE are HIGH). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. MODE REGISTER SET (MRS or EMRS) The mode registers are loaded via bank address and address inputs. The bank address balls determine which mode register will be programmed. See sections on Mode Register and Extended Mode Register. The MRS and EMRS commands can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. ACTIVATE The ACTIVATE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the bank address inputs determines the bank, and the address inputs select the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the bank address inputs determine the bank, and the address provided on address inputs A0–A9 (x8) or A0–A8 (x16) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. DDR2 SDRAM also supports the AL feature, which allows a READ or WRITE command to be issued prior to tRCD (MIN) by delaying the actual registration of the READ/WRITE command to the internal device by AL clock cycles. WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the bank select inputs selects the bank, and the address provided on inputs A0–A9 (x8) or A0–A8 (x16) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. DDR2 SDRAM also supports the AL feature, which allows a READ or WRITE command to be issued prior to tRCD (MIN) by delaying the actual registration of the READ/WRITE command to the internal device by AL clock cycles. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. ...

Page 44

IS43/46DR83200A, IS43/46DR16160A PREChARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row activation a specified time (tRP) after the PRECHARGE command is issued, except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. After a bank has been precharged the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle state the previously open row is already in the process of precharging. However, the precharge period will be determined by the last PRECHARGE command issued to the bank. REFRESh REFRESH is used during normal operation of the DDR2 SDRAM and is analogous to CAS-before-RAS (CBR) REFRESH. All banks must be in the idle mode prior to issuing a REFRESH command. This command is nonpersistent must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a “Don’t Care” during a REFRESH command. SELF REFRESh The SELF REFRESH command can be used to retain data in the DDR2 SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR2 SDRAM retains data without external clocking. All power supply inputs (including VREF) must be maintained at valid levels upon entry/exit and during SELF REFRESH operation. The SELF REFRESH command is initiated like a REFRESH command except CKE is LOW. The DLL is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh. ODT (On-Die Termination) The On-Die Termination feature allows the DDR2 SDRAM to easily implement a termination resistance (Rtt) for each DQ, DQS, DQS, RDQS, and RDQS signal. The ODT feature can be configured with the Extended Mode Register Set (EMRS) command, and turned on or off using the ODT input signal. Before and after the EMRS is issued, the ODT input must be received with respect to the timings of tAOFD, tMOD(max), tAOND; and the CKE input must be held HIGH throughout the duration of tMOD(max). The DDR2 SDRAM supports the ODT on and off functionality in Active, Standby, and Power Down modes, but not in Self Refresh mode. ODT timing diagrams follow for Active/Standby mode and Power Down mode. EMRS to ODT Update Delay CMD E MRS CK ...

Page 45

IS43/46DR83200A, IS43/46DR16160A ODT On/Off Timing for Active/Standby mode CKE (ac) ODT IH t AOND ODT On/Off Timing for Power-Down mode CKE ODT (ac) ...

Page 46

... IS43DR16160A-25EBL 5-5-5 IS43DR16160A-3DBL 4-4-4 IS43DR16160A-37CBL C, T  = -40 C to +85 C   6-6-6 IS43DR16160A-25EBLI 5-5-5 IS43DR16160A-3DBLI IS43DR16160A-3DBI 4-4-4 IS43DR16160A-37CBLI 3-3-3 IS43DR16160A-5BBLI C to +95 C, T  = -40 C to + 4-4-4 IS46DR16160A-37CBLA1 IS46DR16160A-37CBA1 3-3-3 IS46DR16160A-5BBLA1 C to +105 C, T   ...

Page 47

IS43/46DR83200A, IS43/46DR16160A Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 04/08/2011 47 ...

Page 48

IS43/46DR83200A, IS43/46DR16160A 48 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 04/08/2011 ...