IS43DR16160A-37CBL INTEGRATED SILICON SOLUTION (ISSI), IS43DR16160A-37CBL Datasheet - Page 42

• Manufacturer Part Number: IS43DR16160A-37CBL
• Description: SDRAM, DDR2, 16M X 16, 1.8V, 84BGA
• Manufacturer: INTEGRATED SILICON SOLUTION (ISSI)

Specifications of IS43DR16160A-37CBL

• Access Time: 450ps
• Page Size: 256Mbit
• Memory Case Style: BGA
• No. Of Pins: 84
• Memory Type: SDRAM
• Memory Configuration: 4 BLK (4M X 16)
• Operating Temperature Range: 0°C To +70°C
• Frequency: 266MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS43/46DR83200A, IS43/46DR16160A
Clock Enable (CKE) Truth Table
Notes:
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N).
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands
6. Self Refresh mode can only be entered from the All Banks Idle state.
7. Must be a legal command as defined in the Command Truth Table.
8. Valid commands for Power Down Entry and Exit are NOP and DESELECT only.
9. Valid commands for Self Refresh Exit are NOP and DESELECT only.
10. Power Down and Self Refresh cannot be entered while Read or Write operations, (Extended) Mode Register Set operations or Precharge
11. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
13. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh requirements
14. CKE must be maintained HIGH while the DDRII SDRAM is in OCD calibration mode .
15. “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in
16. VREF must be maintained during Self Refresh operation.
Data Mask Truth Table
Note:
1. Used to mask write data, provided coincident with the corresponding data
42
Current
State
Power Down
Self Refresh
Bank(s)
Active
All Banks
Idle
Name (Functional)
Write enable
Write inhibit
may be issued only after tXSRD (200 clocks) is satisfied.
operations are in progress.
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the
time period of tIS + 2 x tCK + tIH.
outlined in this datasheet.
Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMR(1) ).
2
Previous Cycle
(N-1)
H
H
H
H
L
L
L
L
DM
H
L
CKE
1
Current Cycle
Valid
DQs
X
(N)
H
H
H
L
L
L
L
L
Note
1
1
1
RAS, CAS, WE,
Command (N)
DESELECT or
DESELECT or
DESELECT or
DESELECT or
REFRESH
NOP
NOP
NOP
NOP
CS
Refer to the Command Truth Table
X
X
3
Integrated Silicon Solution, Inc. — www.issi.com
Active Power Down Entry
Precharge Power Down
Maintain Power-Down
Maintain Self Refresh
Self Refresh Entry
Power Down Exit
Self Refresh Exit
Action (N)
Entry
3
Notes
11, 13, 15
4, 8, 11, 13
11, 15,16
4, 5, 9, 16
4, 8, 10, 11, 13
4, 8, 10, 11,13
6, 9, 11,13
7
04/08/2011
Rev. A