IS61LPS25636A-200TQLI INTEGRATED SILICON SOLUTION (ISSI), IS61LPS25636A-200TQLI Datasheet
IS61LPS25636A-200TQLI
Specifications of IS61LPS25636A-200TQLI
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IS61LPS25636A-200TQLI Summary of contents
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A 256K x 36, 256K x 32, 512K SYNCHRONOUS PIPELINED, SINgLE CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A BLOCK DIAGRAM CLK ADV ADSC ADSP 18/ BWE BW(a-d) x18: a,b x32/x36: a-d CE CE2 CE2 POWER ZZ DOWN OE 2 MODE A0' Q0 CLK A0 BINARY COUNTER A1 CLR MEMORY ARRAY 16/17 18/ ADDRESS REGISTER CE CLK 32, 36 DQ(a-d) BYTE WRITE REGISTERS CLK ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A 165-PIN BgA 165-Ball, 13x15 mm BGA 1mm Ball Pitch, 11x15 Ball Array BOTTOM VIEW Integrated Silicon Solution, Inc. Rev. K 01/19/10 119-PIN BgA 119-Ball, 14x22 mm BGA 1mm Ball Pitch, 7x17 Ball Array BOTTOM VIEW 3 ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A 119 BGA PACKAGE PIN CONFIGURATION DDQ B NC CE2 DQc DQPc Vss E DQc DQc Vss F V DQc Vss DDQ g DQc DQc BWc H DQc DQc Vss DDQ DD K DQd DQd Vss L DQd DQd BWd M V DQd Vss ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A 119 BGA PACKAGE PIN CONFIGURATION 512k 18 (TOP VIEW DDQ B NC CE2 DQb DQb DDQ g NC DQb H DQb DDQ DQb L DQb DQb DDQ N DQb DQPb TMS DDQ Note and A are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A 165 PBGA PACKAGE PIN CONFIGURATION 256k 36 (TOP VIEW CE2 C DQPc NC V ddq D DQc DQc V ddq E DQc DQc V ddq F DQc DQc V ddq g DQc DQc V ddq H NC Vss NC J DQd DQd V ddq K DQd DQd V ddq L DQd DQd ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A 165 PBGA PACKAGE PIN CONFIGURATION 512k 18 (TOP VIEW CE2 ddq D NC DQb V ddq E NC DQb V ddq F NC DQb V ddq g NC DQb V ddq H NC Vss NC J DQb NC V ddq K DQb NC V ddq L DQb NC V ddq M DQb ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A PIN CONFIGURATION 100 DQPc 1 DQc 2 DQc 3 VDDQ 4 VSS 5 DQc 6 DQc 7 DQc 8 DQc 9 10 VSS 11 VDDQ 12 DQc 13 DQc VDD VSS 18 DQd 19 DQd 20 VDDQ 21 VSS 22 DQd 23 DQd 24 DQd DQd 25 VSS 26 VDDQ 27 DQd 28 DQd 29 DQPd Chip-Enable option) PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A PIN CONFIGURATION 100 DQc 3 DQc 4 VDDQ 5 VSS 6 DQc DQc 7 DQc 8 DQc 9 VSS 10 VDDQ 11 DQc 12 DQc VDD VSS 18 DQd 19 DQd 20 VDDQ 21 VSS 22 DQd 23 DQd 24 DQd 25 DQd 26 VSS 27 VDDQ 28 DQd 29 DQd Chip-Enable option) PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A PIN CONFIGURATION 100 VDDQ 5 VSS DQb DQb 9 10 VSS VDDQ 11 12 DQb 13 DQb VDD 16 NC VSS 17 18 DQb DQb 19 20 VDDQ 21 VSS DQb 22 23 DQb 24 DQPb VSS VDDQ Chip-Enable Option) PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A TRUTH TABLE (1-8) OPERATION ADDRESS CE CE2 Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Snooze Mode, Power-Down None Read Cycle, Begin Burst External ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A INTERLEAVED BURST ADDRESS TABLE (MODE = V External Address 1st Burst Address LINEAR BURST ADDRESS TABLE (MODE = VSS) A1', A0' = 1,1 ABSOLUTE MAxIMUM RATINgS Symbol Parameter T Storage Temperature sTg P Power Dissipation d I Output Current (per I/O) OuT Voltage Relative to Vss for I/O Pins ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A OPERATINg RANgE (IS61LPSxxxxx) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C OPERATINg RANgE (IS61VPSxxxxx) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C OPERATINg RANgE (IS64LPSxxxxx) Range Ambient Temperature Automotive – ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions I AC Operating Device Selected ≤ V Supply Current All Inputs ≤ 0.2V or ≥ V – 0.2V, dd Cycle Time ≥ Standby Current Device Deselected, sb TTL Input V = Max., dd All Inputs ≤ ≤ Max ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A CAPACITANCE (1,2) Symbol Parameter c Input Capacitance IN c Input/Output Capacitance OuT Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions 25° MHz 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load 2.5 I/O OUTPUT LOAD EQUIVALENT Z = 50Ω O Output Figure 3 16 Unit 0V to 2.5V 1 ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A READ/WRITE CYCLE SWITCHINg CHARACTERISTICS Symbol Parameter f Clock Frequency MAx t Cycle Time kc t Clock High Time kh t Clock Low Time kl t Clock Access Time kq t Clock High to Output Invalid (2) kqx t Clock High to Output Low-Z (2,3) kqlZ ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A READ/WRITE CYCLE TIMINg t KC CLK ADSP t SS ADSC ADV Address RD1 BWE BWx t t CES CEH CES CEH CE2 t t CES CEH CE2 t OEQ OE t OELZ High-Z DATA OUT t KQLZ t KQ High-Z DATA IN Single Read ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A WRITE CYCLE TIMINg t KC CLK ADSP ADSC ADV must be inactive for ADSP Write ADV Address WR1 BWE WR1 BWx t t CES CEH CES CEH CE2 t t CES CEH CE2 OE High-Z DATA OUT t DS High-Z DATA ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A SNOOZE MODE ELECTRICAL CHARACTERISTICS Symbol Parameter I Current during SNOOZE MODE active to input ignored Pds t ZZ inactive to input sampled Pus t ZZ active to SNOOZE current ZZI t ZZ inactive to exit SNOOZE current rZZI SNOOZE MODE TIMINg CLK t PDS ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAg) The IS61LPS/VPSxxxxxx products have a serial boundary scan Test Access Port (TAP) in the PBGA package only. (The TQFP package not available.) This port operates in accordance with IEEE Standard 1149.1-1900, but does not include all functions required for full 1149 ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A TEST DATA OUT (TDO) The TDO output pin is used to serially clock data-out from the registers.The output is active depending on the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK and TDO is connected to the Least Significant Bit (LSB) of any register ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A TAP INSTRUCTION SET Eight instructions are possible with the three-bit instruction register and all combinations are listed in the Instruction Code table. Three instructions are listed as RESERVED and should not be used and the other five instructions are described below ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A INSTRUCTION CODES Code Instruction Description 000 EXTEST Captures the Input/Output ring contents. Places the boundary scan register be- tween the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. 001 IDCODE Loads the ID register with the vendor ID code and places the register between TDI and TDO ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A TAP Electrical Characteristics Over the Operating Range Symbol Parameter V Output HIGH Voltage Oh1 V Output HIGH Voltage Oh2 V Output LOW Voltage Ol1 V Output LOW Voltage Ol2 V Input HIGH Voltage Ih V Input LOW Voltage Il I Input Leakage Current ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A TAP AC TEST CONDITIONS (2.5V/3.3V) Input pulse levels 0 to 2.5V/0 to 3.0V Input rise and fall times Input timing reference levels Output reference levels Test load termination supply voltage Vtrig TAP TIMINg 1 t THTH TCK t MVTH TMS ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A 119 BgA BOUNDARY SCAN ORDER (256K x 36) Signal Bump Bit # Name ID Bit # DQa DQa DQa DQa DQa DQa DQa DQa DQa DQb 6H 36 119 BgA BOUNDARY SCAN ORDER (512K x 18) Signal Bump Bit # Name ID Bit # ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A 165 PBgA BOUNDARY SCAN ORDER (x 36) Signal Bump Bit # Name ID Bit # 1 MODE 11P 10P 10R 11R 11H 31 12 DQa 11N 32 13 DQa 11M 33 14 DQa 11L 34 15 DQa 11K 35 16 DQa 11J 36 17 DQa 10M ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A 165 PBgA BOUNDARY SCAN ORDER (x 18) Signal Bump Bit # Name ID Bit # 1 MODE 11P 10P 10R 11R 11H 11N 11M 11L 11K 11J 36 17 DQa 10M 37 18 DQa 10L 38 19 DQa 10K 39 20 DQa 10J 40 Integrated Silicon Solution, Inc. ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A ORDERINg INFORMATION (3.3V core/2.5V-3.3V I/O) Commercial Range: 0°C to +70°C Configuration Frequency 256Kx36 250 200 166 512Kx18 250 200 30 Order Part Number Package IS61LPS25636A-250TQ 100 TQFP, 3CE IS61LPS25636A-250B2 119 PBGA IS61LPS25636A-250B3 165 PBGA IS61LPS25636A-200TQ 100 TQFP, 3CE ...
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... Automotive Range: -40°C to +125°C Configuration Frequency 256Kx36 166 Integrated Silicon Solution, Inc. Rev. K 01/19/10 Order Part Number IS61LPS25632A-200TQLI IS61LPS25636A-250TQI IS61LPS25636A-250TQLI IS61LPS25636A-250B2I IS61LPS25636A-250B3I IS61LPS25636A-200TQI IS61LPS25636A-200TQ2I IS61LPS25636A-200TQLI IS61LPS25636A-200B2I IS61LPS25636A-200B2LI IS61LPS25636A-200B3I IS61LPS25636A-200B3LI IS61LPS25636A-166TQLI IS61LPS51218A-250TQI IS61LPS51218A-250B2I IS61LPS51218A-250B3I IS61LPS51218A-200TQI IS61LPS51218A-200TQ2I IS61LPS51218A-200TQLI IS61LPS51218A-200B2I IS61LPS51218A-200B3I Order Part Number IS64LPS25636A-166TQLA3 ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A ORDERINg INFORMATION (2.5V core/2.5V I/O) Commercial Range: 0°C to +70°C Configuration Frequency 256Kx36 250 200 512Kx18 250 200 Industrial Range: -40°C to +85°C Configuration Frequency 256Kx36 250 200 512Kx18 250 200 Note: 1. For 100 TQFP, 2CE option contact SRAM Marketing at sram@issi.com ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A Integrated Silicon Solution, Inc. Rev. K 01/19/10 33 ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A 34 Integrated Silicon Solution, Inc. Rev. K 01/19/10 ...
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... IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A Integrated Silicon Solution, Inc. Rev. K 01/19/10 35 ...