IS61LPS25636A-200TQLI INTEGRATED SILICON SOLUTION (ISSI), IS61LPS25636A-200TQLI Datasheet - Page 24

IC, SRAM, 9MBIT, PARALLEL, 3.1NS TQFP100

IS61LPS25636A-200TQLI

Manufacturer Part Number
IS61LPS25636A-200TQLI
Description
IC, SRAM, 9MBIT, PARALLEL, 3.1NS TQFP100
Manufacturer
INTEGRATED SILICON SOLUTION (ISSI)
Datasheet

Specifications of IS61LPS25636A-200TQLI

Memory Size
8Mbit
Memory Configuration
256K X 36
Clock Frequency
200MHz
Access Time
3.1ns
Supply Voltage Range
3.135V To 3.465V
Memory Case Style
TQFP
No. Of Pins
100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IS61LPS25636A-200TQLI
Manufacturer:
ISSI
Quantity:
1 000
Part Number:
IS61LPS25636A-200TQLI
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Part Number:
IS61LPS25636A-200TQLI
Manufacturer:
ISSI
Quantity:
20 000
Company:
Part Number:
IS61LPS25636A-200TQLI
Quantity:
7
Part Number:
IS61LPS25636A-200TQLI-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Part Number:
IS61LPS25636A-200TQLI-TR
Manufacturer:
ISSI
Quantity:
20 000
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
INSTRUCTION CODES
TAP CONTROLLER STATE DIAgRAM
24
Code
000
001
010
011
100
101
110
111
SAMPLE/PRELOAD
RESERVED
RESERVED
RESERVED
Instruction
SAMPLE-Z
EXTEST
IDCODE
BYPASS
1
0
Test Logic Reset
Run Test/Idle
0
Description
Captures the Input/Output ring contents. Places the boundary scan register be-
tween the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation. This instruction does not
implement 1149.1 preload function and is therefore not 1149.1 compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
1
1
0
1
Capture DR
Update DR
Select DR
Pause DR
Exit1 DR
Exit2 DR
Shift DR
0
1
1
1
0
0
0
0
0
1
1
1
0
1
Capture IR
Update IR
Select IR
Pause IR
Exit1 IR
Exit2 IR
Shift IR
0
Integrated Silicon Solution, Inc.
1
1
0
1
0
0
0
0
1
1
01/19/10
Rev. K

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