PIC16F1826-I/MQ Microchip Technology, PIC16F1826-I/MQ Datasheet - Page 209

• Manufacturer Part Number: PIC16F1826-I/MQ
• Description: IC, 8BIT MCU, PIC16F, 32MHZ, QFN-28
• Manufacturer: Microchip Technology

Specifications of PIC16F1826-I/MQ

• Controller Family/series: PIC16F
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 32MHz
• No. Of Timers: 3
• Interface: EUSART, I2C, SPI
• Core Size: 8 Bit
• Program Memory Size: 2kWords
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.4
In Compare mode, the 16-bit CCPRx register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the CCPx module may:
• Toggle the CCPx output
• Set the CCPx output
• Clear the CCPx output
• Generate a Special Event Trigger
• Generate a Software Interrupt
The action on the pin is based on the value of the
CCPxM<3:0> control bits of the CCPxCON register. At
the same time, the interrupt flag CCPxIF bit is set.
All Compare modes can generate an interrupt.
FIGURE 23-2:
23.4.1
The user must configure the CCPx pin as an output by
clearing the associated TRIS bit.
Also, the CCPx pin function can be moved to
alternative pins using the APFCON register. Refer to
Section 12.1 “Alternate Pin Function” for more
details.
© 2009 Microchip Technology Inc.
Note:
CCPx
Pin
Output Enable
TRIS
Compare Mode
CCPX PIN CONFIGURATION
Clearing the CCPxCON register will force
the CCPx compare output latch to the
default low level. This is not the PORT I/O
data latch.
Q
Special Event Trigger
CCPxCON<3:0>
R
S
Mode Select
Output
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Logic
Set CCPxIF Interrupt Flag
4
(PIRx)
Match
CCPRxH CCPRxL
TMR1H
Comparator
TMR1L
Preliminary
23.4.2
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
23.4.3
When Generate Software Interrupt mode is chosen
(CCPxM<3:0> = 1010), the CCPx module does not
assert control of the CCPx pin (see the CCP1CON
register).
23.4.4
When Special Event Trigger mode is chosen
(CCPxM<3:0> = 1011), the CCPx module does the
following:
• Resets Timer1
• Starts an ADC conversion if ADC is enabled
The CCPx module does not assert control of the CCPx
pin in this mode (see the CCPxCON register).
The Special Event Trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and the CCPRxH, CCPRxL
register pair. The TMR1H, TMR1L register pair is not
reset until the next rising edge of the Timer1 clock.
The Special Event Trigger output starts an A/D
conversion (if the A/D module is enabled). This feature
is only available on CCP4 for PIC16F/LF1827 and
ECCP1 on PIC16F/LF1826. This allows the CCPRxH,
CCPRxL register pair to effectively provide a 16-bit
programmable period register for Timer1.
23.4.5
The Compare mode is dependent upon the system
clock (F
down during Sleep mode, the Compare mode will not
function properly during Sleep.
Note:
Note 1: The Special Event Trigger from the CCP
PIC16F/LF1826/27
OSC
2: Removing
TIMER1 MODE SELECTION
Clocking Timer1 from the system clock
(F
mode. In order for Capture mode to
recognize the trigger event on the CCPx
pin, TImer1 must be clocked from the
instruction clock (F
external clock source.
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
COMPARE DURING SLEEP
) for proper operation. Since F
module does not set interrupt flag bit
TMR1IF of the PIR1 register.
changing the contents of the CCPRxH
and CCPRxL register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates the Timer1 Reset, will preclude
the Reset from occurring.
OSC
) should not be used in Capture
the
match
OSC
DS41391B-page 209
/4) or from an
condition
OSC
is shut
by