PIC16F1826-I/MQ Microchip Technology, PIC16F1826-I/MQ Datasheet - Page 71

• Manufacturer Part Number: PIC16F1826-I/MQ
• Description: IC, 8BIT MCU, PIC16F, 32MHZ, QFN-28
• Manufacturer: Microchip Technology

Specifications of PIC16F1826-I/MQ

• Controller Family/series: PIC16F
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 32MHz
• No. Of Timers: 3
• Interface: EUSART, I2C, SPI
• Core Size: 8 Bit
• Program Memory Size: 2kWords
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.0
The reference clock module provides the ability to send
a divided clock to the clock output pin of the device
(CLKR) and provide a secondary internal clock source
to the modulator module. This module is available in all
oscillator configurations and allows the user to select a
greater range of clock submultiples to drive external
devices in the application. The reference clock module
includes the following features:
• System clock is the source
• Available in all oscillator configurations
• Programmable clock divider
• Output enable to a port pin
• Selectable duty cycle
• Slew rate control
The reference clock module is controlled by the
CLKRCON register (Register 6-1) and is enabled when
setting the CLKREN bit. To output the divided clock sig-
nal to the CLKR port pin, the CLKROE bit must be set.
The CLKRDIV<2:0> bits enable the selection of 8 dif-
ferent clock divider options. The CLKRDC<1:0> bits
can be used to modify the duty cycle of the output
clock
For information on using the reference clock output
with the modulator module, see Section 22.0 “Data
Signal Modulator”.
6.1
When a reference clock signal of 20 MHz or greater is
required, the slew rate limitation on the output port pin
can be disabled. The slew rate limitation can be
removed by clearing the CLKRSLR bit in the
CLKRCON register.
6.2
Upon any device Reset, the reference clock module is
disabled. The user’s firmware is responsible for
initializing the module before enabling the output. The
registers are reset to their default values.
© 2009 Microchip Technology Inc.
Note 1: If the base clock rate is selected without a
(1)
. The CLKRSLR bit controls slew rate limiting.
REFERENCE CLOCK MODULE
Slew rate
Effects of a Reset
divider, the output clock will always have
a duty cycle equal to that of the source
clock, unless a 0% duty cycle is selected.
If the clock divider is set to base clock/2,
then 25% and 75% duty cycle accuracy
will be dependent upon the source clock.
Preliminary
6.3
There are two cases when the reference clock output
signal cannot be output to the CLKR pin, if:
• LP, XT, or HS oscillator mode is selected.
• CLKOUT function is enabled.
Even if either of these cases are true, the module can
still be enabled and the reference clock signal may be
used in conjunction with the modulator module.
6.3.1
If LP, XT, or HS oscillator modes are selected, the
OSC2/CLKR pin must be used as an oscillator input pin
and the CLKR output cannot be enabled. See
Section 5.2 “Clock Source Types” for more informa-
tion on different oscillator modes.
6.3.2
The CLKOUT function has a higher priority than the ref-
erence clock module. Therefore, if the CLKOUT func-
tion is enabled by the CLKOUTEN bit in Configuration
Word 1, F
Reference Section 4.0 “Device Configuration” for
more information.
6.4
As the reference clock module relies on the system
clock as its source, and the system clock is disabled in
Sleep, the module does not function in Sleep, even if
an external clock source or the Timer1 clock source is
configured as the system clock. The module outputs
will remain in their current state until the device exits
Sleep.
PIC16F/LF1826/27
Conflicts with the CLKR pin
Operation During Sleep
OSC
OSCILLATOR MODES
CLKOUT FUNCTION
/4 will always be output on the port pin.
DS41391B-page 71