PIC16LF819T-I/SSTSL Microchip Technology, PIC16LF819T-I/SSTSL Datasheet - Page 165

• Manufacturer Part Number: PIC16LF819T-I/SSTSL
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF819T-I/SSTSL

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC16LF819TISSTSL

15.2
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTA<4>). In this mode, the
EUSART uses the standard Non-Return-to-Zero (NRZ)
format (one Start bit, eight or nine data bits and one
Stop bit). The most common data format is eight bits.
An on-chip dedicated 8-bit/16-bit Baud Rate Generator
can be used to derive standard baud rate frequencies
from the oscillator.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent but use the same data format and baud
rate. The Baud Rate Generator produces a clock,
either x16 or x64 of the bit shift rate depending on the
BRGH
BAUDCON<3>). Parity is not supported by the hard-
ware but can be implemented in software and stored as
the ninth data bit.
When operating in Asynchronous mode, the EUSART
module consists of the following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
• Auto-Wake-up on Sync Break Character
• 12-Bit Break Character Transmit
• Auto-Baud Rate Detection
15.2.1
The EUSART transmitter block diagram is shown in
Figure 15-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREG register (if available).
FIGURE 15-3:
© 2008 Microchip Technology Inc.
EUSART Asynchronous Mode
and
BRG16
EUSART ASYNCHRONOUS
TRANSMITTER
TXIE
BRG16
Interrupt
EUSART TRANSMIT BLOCK DIAGRAM
SPBRGH
Baud Rate Generator
TXIF
TXEN
bits
Baud Rate CLK
SPBRG
(TXSTA<2>
MSb
(8)
and
TXREG Register
TSR Register
TX9D
• • •
TX9
8
Data Bus
Once the TXREG register transfers the data to the TSR
register (occurs in one T
empty and the TXIF flag bit (PIR1<4>) is set. This inter-
rupt can be enabled or disabled by setting or clearing
the interrupt enable bit, TXIE (PIE1<4>). TXIF will be
set regardless of the state of TXIE; it cannot be cleared
in software. TXIF is also not cleared immediately upon
loading TXREG but becomes valid in the second
instruction cycle following the load instruction. Polling
TXIF immediately following a load of TXREG will return
invalid results.
While TXIF indicates the status of the TXREG register,
another bit, TRMT (TXSTA<1>), shows the status of
the TSR register. TRMT is a read-only bit which is set
when the TSR register is empty. No interrupt logic is
tied to this bit so the user has to poll this bit in order to
determine if the TSR register is empty.
To set up an Asynchronous Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
Note 1: The TSR register is not mapped in data
Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
If interrupts are desired, set enable bit, TXIE.
If 9-bit transmission is desired, set transmit bit,
TX9. Can be used as address/data bit.
Enable the transmission by setting bit, TXEN,
which will also set bit, TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
Load data to the TXREG register (starts
transmission).
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
LSb
2: Flag bit, TXIF, is set when enable bit,
0
PIC18F2450/4450
memory so it is not available to the user.
TXEN, is set.
TRMT
and Control
Pin Buffer
SPEN
CY
), the TXREG register is
DS39760D-page 163
TX pin