PIC16LF819T-I/SSTSL Microchip Technology, PIC16LF819T-I/SSTSL Datasheet - Page 174

• Manufacturer Part Number: PIC16LF819T-I/SSTSL
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF819T-I/SSTSL

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC16LF819TISSTSL

Synchronous Master mode in that the shift clock is
PIC18F2450/4450
15.4
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA<7>). This mode differs from the
supplied externally at the CK pin (instead of being
supplied internally in Master mode). This allows the
device to transfer or receive data while in any low-power
mode.
15.4.1
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep mode.
If two words are written to the TXREG register and then
the SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
TABLE 15-9:
DS39760D-page 172
INTCON
PIR1
PIE1
IPR1
RCSTA
TXREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Name
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in the TXREG
register.
Flag bit, TXIF, will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit, TXIF, will now be set.
If enable bit, TXIE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
EUSART Synchronous
Slave Mode
EUSART SYNCHRONOUS
SLAVE TRANSMIT
EUSART Transmit Register
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL
ABDOVF
CSRC
SPEN
Bit 7
—
—
—
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
RCIDL
ADIE
ADIP
ADIF
Bit 6
RX9
TX9
TMR0IE
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
—
INT0IE
CREN
SYNC
SCKP
TXIE
TXIP
Bit 4
TXIF
ADDEN
SENDB
BRG16
To set up a Synchronous Slave Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
RBIE
Bit 3
—
—
—
Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
Clear bits, CREN and SREN.
If interrupts are desired, set enable bit, TXIE.
If 9-bit transmission is desired, set bit, TX9.
Enable the transmission by setting enable bit,
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TMR0IF
CCP1IF
CCP1IE
CCP1IP
BRGH
FERR
Bit 2
—
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
WUE
Bit 1
© 2008 Microchip Technology Inc.
TMR1IF
TMR1IE
TMR1IP
ABDEN
RX9D
TX9D
RBIF
Bit 0
on Page:
Values
Reset
49
51
51
51
51
51
51
51
50
50