PIC16LF819T-I/SSTSL Microchip Technology, PIC16LF819T-I/SSTSL Datasheet - Page 256

IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC

PIC16LF819T-I/SSTSL

Manufacturer Part Number
PIC16LF819T-I/SSTSL
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16LF819T-I/SSTSL

Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC16LF819TISSTSL
PIC18F2450/4450
XORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39760D-page 254
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
W
REG
W
Q1
=
=
=
=
register ‘f’
Exclusive OR W with f
XORWF
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) .XOR. (f) → dest
N, Z
Exclusive OR the contents of W with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in the register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
XORWF
Read
0001
Q2
AFh
B5h
1Ah
B5h
REG, 1, 0
f {,d {,a}}
10da
Process
Data
Q3
ffff
destination
Write to
Q4
ffff
© 2008 Microchip Technology Inc.

Related parts for PIC16LF819T-I/SSTSL