IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 118

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–34
Table 5–14. Configuration Space Signals (Hard IP Implementation) (Part 1 of 2)
PCI Express Compiler User Guide
Signal
tl_cfg_add
tl_cfg_ctl
Width Dir Description
4
32
In the example design created with the PCI Express IP core, there is a Verilog HDL
module or VHDL entity included in the altpcierd_tl_cfg_sample.v and
altpcierd_tl_cfg_sample.vhd files respectively that you can use to sample the
configuration space signals. In this module or entity the tl_cfg_ctl_wr and
tl_cfg_sts_wr signals are registered twice and then the edges of the delayed signals
are used to enable sampling of the tl_cfg_ctl and tl_cfg_sts busses.
Because the hard IP core_clk is much earlier than the pld_clk, the Quartus II
software tries to add delay to the signals to avoid hold time violations. This delay is
only necessary for the tl_cfg_ctl_wr and tl_cfg_sts_wr signals. You can place
multicycle setup and hold constraints of three cycles on them to avoid timing issues if
the logic shown in
contraints are automatically included in the <variation_name>.sdc file that is created
with the hard IP variation. In some cases, depending on the exact device, speed grade
and global routing resources used for the pld_clk, the Quartus II software may have
difficulty avoiding hold time violations on the tl_cfg_ctl_wr and tl_cfg_sts_wr
signals. If hold time violations occur in your design, you can reduce the multicycle
setup time for these signals to 0. The exact time the signals are clocked is not critical to
the design, just that the signals are reliably sampled. There are instruction comments
in the <variation_name>.sdc file on making these modifications.
Stratix V Hard IP Implementation
Table 5–14
Stratix V devices. For Stratix V devices, tl_cfg_add, tl_cfg_ctl, and tl_cfg_sts are
updated every pld_clk cycle
0
0
describes the configuration space signals for the hard IP implementation in
Address of the register that has been updated. This address space is described in
Table 5–15 on page
The tl_cfg_ctl signal is multiplexed and contains the contents of the configuration
space registers as shown in this table. This register carries data that updates every
pld_clk cycle.
Figure 5–30
5–36. The information updates every pld_clk cycle.
and
Figure 5–32
is used. The multicycle setup and hold
December 2010 Altera Corporation
Chapter 5: IP Core Interfaces
Avalon-ST Interface