IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 344
IP-AGX-PCIE/4
Manufacturer Part Number
IP-AGX-PCIE/4
Description
IP CORE - PCI Express X1 And X4 Lanes For Arria GX
Manufacturer
Altera
Datasheet
1.IP-AGX-PCIE1.pdf
(362 pages)
Specifications of IP-AGX-PCIE/4
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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C–2
PCI Express Compiler User Guide
Arria II GX Devices
Stratix II GX Devices
Table C–2
Arria II GX (EP2AGX125EF35C4) devices for different parameters with a maximum
payload of 256 bytes using the Quartus II software, version 10.1.
Table C–2. Performance and Resource Utilization, Avalon-ST Interface–Arria GX Devices
Table C–3
Stratix II and Stratix II GX (EP2SGX130GF1508C3) devices for a maximum payload of
256 bytes for devices with different parameters, using the Quartus II software, version
10.1.
Table C–3. Performance and Resource Utilization, Avalon-ST Interface - Stratix II and
Stratix II GX Devices
Note to
(1) This configuration only supports Gen1.
(Note 1)
×1/ ×4
×1/ ×4
×8
×1
×1
×4
×4
×8
×8
×1
×1
×4
×4
Table
Clock (MHz)
shows the typical expected performance and resource utilization of
shows the typical expected performance and resource utilization of
Clock (MHz)
C–1:
Internal
Parameters
Parameters
Internal
125
125
125
125
250
250
125
125
125
125
Channels
Virtual
Channel
Virtual
1
2
1
2
1
2
1
2
1
2
Combinational
Combinational
ALUTs
5400
7000
6900
8500
6300
7600
ALUTs
5300
6800
6900
8400
Size
Registers
Registers
Logic
4000
5200
4900
6100
5900
7000
Logic
4000
5200
5000
6200
Size
December 2010 Altera Corporation
M512
Memory Blocks
M9K
10
10
14
11
18
2
3
6
7
9
Avalon-ST Interface
Chapter :
M4K
13
19
17
27
15
23
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