IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 93

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Avalon-ST Interface
Table 5–3. Mapping Avalon-ST Packets to PCI Express TLPs
December 2010 Altera Corporation
Header0
Header1
Header2
Header3
Data0
Data1
Data2
Data<n>
Packet
f
f
pcie_hdr_byte0, pcie_hdr _byte1, pcie_hdr _byte2, pcie_hdr _byte3
pcie_hdr _byte4, pcie_hdr _byte5, pcie_hdr byte6, pcie_hdr _byte7
pcie_hdr _byte8, pcie_hdr _byte9, pcie_hdr _byte10, pcie_hdr _byte11
pcie_hdr _byte12, pcie_hdr _byte13, header_byte14, pcie_hdr _byte15
pcie_data_byte3, pcie_data_byte2, pcie_data_byte1, pcie_data_byte0
pcie_data_byte7, pcie_data_byte6, pcie_data_byte5, pcie_data_byte4
pcie_data_byte11, pcie_data_byte10, pcie_data_byte9, pcie_data_byte8
pcie_data_byte<n>, pcie_data_byte<n-1>, pcie_data_byte<n>-2, pcie_data_byte<n-3>
writes, configuration writes, and I/O writes. The alignment of the request TLP
depends on bit 2 of the request address. For completion TLPs with data, alignment
depends on bit 2 of the lower address field. This bit is always 0 (aligned to qword
boundary) for completion with data TLPs that are for configuration read or I/O read
requests.
Figure 5–5. Qword Alignment
Refer to
of all TLPs.
Table 5–3
Figure 5–6–Figure
Figure 5–6
three dword header with non-qword aligned addresses with a 64-bit bus. In this
example, the byte address is unaligned and ends with 0x4, causing the first data to
correspond to rx_st_data[63:32].
For more information about the Avalon-ST protocol, refer to the
Specifications.
Appendix A, Transaction Layer Packet (TLP) Header Formats
shows the byte ordering for header and data packets for
illustrates the mapping of Avalon-ST RX packets to PCI Express TLPs for a
5–13.
0x18
0x10
0x8
0x0
Header
TLP
PCB Memory
Valid Data
64 bits
.
.
.
Addr = 0x4
Valid Data
PCI Express Compiler User Guide
Avalon Interface
for the formats
5–9