IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 181

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 8: Transaction Layer Protocol (TLP) Details
Receive Buffer Reordering
Table 8–2. Transaction Ordering Rules (Part 2 of 2)
December 2010 Altera Corporation
Notes to
(1) CfgRd0 can pass IORd or MRd.
(2) CfgWr0 can IORd or MRd.
(3) CfgRd0 can pass IORd or MRd.
(4) CfrWr0 can pass IOWr.
(5) A Memory Write or Message Request with the Relaxed Ordering Attribute bit clear (b’0) must not pass any other Memory Write or Message
(6) A Memory Write or Message Request with the Relaxed Ordering Attribute bit set (b’1) is permitted to pass any other Memory Write or Message
(7) Endpoints, Switches, and Root Complex may allow Memory Write and Message Requests to pass Completions or be blocked by Completions.
(8) Memory Write and Message Requests can pass Completions traveling in the PCI Express to PCI directions to avoid deadlock.
(9) If the Relaxed Ordering attribute is not set, then a Read Completion cannot pass a previously enqueued Memory Write or Message Request.
(10) If the Relaxed Ordering attribute is set, then a Read Completion is permitted to pass a previously enqueued Memory Write or Message Request.
(11) Read Completion associated with different Read Requests are allowed to be blocked by or to pass each other.
(12) Read Completions for Request (same Transaction ID) must return in address order.
Request.
Request.
Read Completion
I/O or
Configuration
Write
Completion
Table
8–2:
1
MSI requests are conveyed in exactly the same manner as PCI Express memory write
requests and are indistinguishable from them in terms of flow control, ordering, and
data integrity.
1) No
2) Y/N
Y/N
1) No
2) No
No
Yes
Yes
(Note
Yes
Yes
1)–
(12)
Yes
Yes
Yes
Yes
Y/N
1) Y/N
2) No
1) No
2) No
No
PCI Express Compiler User Guide
Y/N
Y/N
No
No
8–5