IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 193

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 10: Interrupts
MSI-X
MSI-X
Legacy Interrupts
December 2010 Altera Corporation
f
Figure 10–4. MSI Interrupt Signals Waveform
Notes to
(1) For variants using the Avalon-ST interface, app_msi_req can extend beyond app_msi_ack before deasserting. For
You can enable MSI-X interrupts by turning on Implement MSI-X on the Capabilities
page using the parameter editor. If you turn on the Implement MSI-X option, you
should implement the MSI-X table structures at the memory space pointed to by the
BARs as part of your application.
MSI-X TLPs are generated by the application and sent through the transmit interface.
They are single dword memory writes so that Last DW Byte Enable in the TLP header
must be set to 4b’0000. MSI-X TLPs should be sent only when enabled by the MSI-X
enable and the function mask bits in the message control for MSI-X configuration
register. In the hard IP implementation, these bits are available on the tl_cfg_ctl
output bus.
For more information about implementing the MSI-X capability structure, refer
Section 6.8.2. of the
Legacy interrupts are signaled on the PCI Express link using message TLPs that are
generated internally by the PCI Express IP core. The app_int_sts input port controls
interrupt generation. When the input port asserts app_int_sts, it causes an
Assert_INTA message TLP to be generated and sent upstream. Deassertion of the
app_int_sts input port causes a Deassert_INTA message TLP to be generated and
sent upstream. Refer to
Figure 10–5
assertion of app_int_ack indicates that the Assert_INTA message TLP has been sent.
Figure 10–5. Legacy Interrupt Assertion
descriptor/data variants, app_msi_req must deassert on the cycle following app_msi_ack
Figure
app_msi_num[4:0]
app_int_ack
app_int_sts
app_msi_tc[2:0]
illustrates interrupt timing for the legacy interface. In this figure the
app_msi_ack
app_msi_req
10–4:
clk
clk
PCI Local Bus Specification, Revision
Figure 10–5
1
2
and
Figure
3
10–6.
valid
valid
3.0.
5
PCI Express Compiler User Guide
6
10–3