IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 131

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Appendix F: Static and Dynamic Phase Alignment
Altera Solutions
December 2010 Altera Corporation
Static Alignment
Dynamic Phase Alignment (DPA)
The Stratix IV, Stratix III, Stratix II, Stratix GX, and Stratix devices have built-in high-
speed interface macros. Using DDR clocking, these macros allow the devices to
receive data at rates exceeding 800 Mbps. Built-in logic within the macros present this
data to the MegaCore
processing. A reference sampling clock recovers the data. This sampling clock is
selected at design time, and cannot be changed when the device is operating.
As high-speed interfaces with source-synchronous clocking schemes approach 700
Mbps and beyond, the margin for clock-to-channel and channel-to-channel skew
contracts significantly. To stay within the permitted budget, designers must use
precise printed circuit board (PCB) design techniques because the slightest mismatch
in trace lengths or the use of connectors could result in erroneous data transfer.
Additionally, skew inducing effects such as process, voltage, and temperature
variations compound the problem, making static phase alignment techniques
ineffective.
DPA technology has been developed to address the inadequacies of static alignment
methods. The goal of DPA is to allow devices to actively respond to changes in the
operational board skew. Devices equipped with DPA continuously check the
incoming data and adjust the phase of the clock to align with it. Several industry
standards responsible for defining chip-to-chip interfaces, including System Packet
Interface (SPI) 4.2, have recognized the value of DPA, and have included or
recommended it in their specifications.
Every Stratix III, Stratix II, and Stratix GX receiver channel features an embedded
DPA block. For Stratix GX devices, the DPA blocks are located in I/O banks 1 and 2;
for Stratix III and Stratix II devices, the DPA blocks are located in banks 1, 2, 5 and 6. A
complete, FPGA-integrated hard-silicon DPA solution offers several benefits to
system designers. It is implemented for each data channel, such that each channel
receives its own phase-adjusted clock. This individual alignment for each channel
minimizes the chance for errors introduced by mismatches in signal propagation
paths. Also, it does not require a training mode; rather, it continuously realigns the
clock to the data during device operation.
The POS-PHY Level 4 MegaCore function utilizes an integrated DPA block on its
receiving path, between the high-speed serial bus and the parallel bus. The functions
of this DPA block include: data deserialization and clock division, dynamic phase
alignment, and byte alignment.
The Stratix GX device family has embedded dynamic phase alignment (DPA) macros
that can support two POS-PHY Level 4 receiver variations in the 1SGX25 and 1SGX40
devices. The 1SGX10 device has a single DPA macro. The Stratix II device family has
embedded DPA macros that can support at least two POS-PHY Level 4 receiver
variations in 2S15, 2S30, and 2S60 devices; or at least four receiver variations in 2S90,
2S130, and 2S180 devices.
The POS-PHY Level 4 DPA block makes use of the DPA capability of Stratix GX
devices, supporting data rates of up to 1 Gbps. The DPA block can be configured to
support 17 hi-speed channels, and internal data widths in excess of 64 or 128 bits.
®
function logic—at lower frequencies—for subsequent protocol
POS-PHY Level 4 MegaCore Function User Guide
F–3