IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 94

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–22
Table 5–8. Data Path and Control Status (Part 1 of 2)
POS-PHY Level 4 MegaCore Function User Guide
ctl_td_holb_disable
stat_td_holb
ctl_td_maxt[15:0]
Signal
Input- Static
reset
Output
Input
Direction
tdint_clk
Clock Domain
Head-of-line blocking disable. When set to logic 1,
the data path requests data from the scheduler or
Atlantic buffer(s) whenever possible. When set to
logic 0, status (after error checking) is monitored for
all ports, and while any port is satisfied, the
transmitter stops requesting data from the scheduler
or Atlantic buffer(s), and sends idle control words or
training patterns. This input is tied to one in the IP
Toolbench top-level file, if you use the individual
buffers mode. Only change at reset.
Indicates if the MegaCore function is currently head-
of-line blocked. It is never asserted if
ctl_td_holb_disable is set to logic 1.
Training sequence interval, measured from the end of
the last training sequence to the beginning of the next
training sequence. The actual interval may be slightly
longer to maintain valid bursts according to
ctl_td_burstlen. Setting to zero disables interval
training insertion. Training is always inserted if
stat_ts_sync is deasserted. Training patterns
always begin on the positive edge of tdclk. Only
change at reset.
Chapter 5: Functional Description—Transmitter
Description
December 2010 Altera Corporation
Signals