IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 80

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–8
Figure 5–3. Example Timing Diagram for the Status Bypass Port
Clock Structure
POS-PHY Level 4 MegaCore Function User Guide
stat_ts_extstat_adr
Single Clock Domain
stat_ts_dip2state
stat_ts_disabled
stat_ts_frmstate
stat_ts_extstat
stat_ts_sync
1
tsclk
Figure 5–3 on page 5–8
With the Atlantic FIFO clock mode parameter in IP Toolbench, you can parameterize
the transmitter in one of the following two clocking structures:
■
■
All data path width variations of the MegaCore function use a common clocking
structure.
All clocks are asynchronous and paths between the domains can be cut.
The transmitter has three primary clock domains.
The first primary clock domain is associated with the SPI-4.2 transmit status channel
and is controlled by the tsclk input. All of the logic pertaining to the SPI-4.2 status
channel processing is controlled by this clock.
The second primary clock domain is a a common clock, tdint_clk, which the
MegaCore function’s protocol logic and all Atlantic FIFO buffers share. This
tdint_clk clocks both the write and read sides of the Atlantic FIFO buffers. The
tdint_clk is an output of the MegaCore function, and is derived from trefclk via the
phase-locked loop (PLL) in the transmit altlvds block.
The third primary clock domain relays received transmit status channel information
to the user logic. This clock domain is controlled by the txsys_clk signal. In most
applications, txsys_clk is on the same domain as tdint_clk, but they are separated
for flexibility.
In the single clock domain mode, the Atlantic FIFO buffers are instantiated as single
clock domain buffers, thereby consuming fewer logic resources.
Single clock domain
Multiple clock domain
3
2'b00 2'b00
3
0
2'b00
0
2'b01
gives an example of the timing for the status bypass port.
0
2'b02
0
2'b03
3
2'b00
3
2'b00
0
2'b00
Chapter 5: Functional Description—Transmitter
0
2'b01
December 2010 Altera Corporation
0
2'b02 2'b03
0
3
2'b00
Clock Structure