IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 83

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Description—Transmitter
Reset Structure
Figure 5–5. Clock Layout Diagram (Quarter Rate)
Reset Structure
Error Flagging and Handling
December 2010 Altera Corporation
SPI-4.2 Error Detection and Handling
ctl_ts_statedge
1
tdat[15:0]
tstat[1:0]
trefclk
tsclk
tdclk
tctl
The SPI-4.2 tdclk is not a separate clock domain because it is not on an FPGA clock
signal. Instead, alternating 1s and 0s are preloaded into the tdclk serializer. As tdclk
is generated using the same PLL as the rest of the data, the clock and data are
launched at the same time. The same technique applies to the 32-bit data path width,
where the ALTLVDS megafunction is set to alternating 1s and 0s for the tdclk signal.
By default, the txreset_n signal is the asynchronous global reset for the MegaCore
function. It is internally metastable hardened and passed to each of the individual
clock domains.
Asserting reset deletes all data in the buffers and resets all of the state bits in the error
checking logic.
In addition to the reset, asynchronous reset and locked signals are provided for the
internal PLL, if present. The PLL should be reset and stable along with all other clocks
before the reset is released.
This section outlines how the POS-PHY Level 4 transmitter MegaCore function
responds to various errors.
The transmitter MegaCore function monitors and decodes the SPI-4.2 input status
channel. When an error is detected, an error flag is asserted. The flag pulses high for
one tsclk period for each error. Errors occur when the received status channel does
not match expectations set by the state machine shown in Figure 6.11 FIFO Status State
Diagram (Sending Side) of the SPI-4.2 Specification.
LVTTL
LVTTL
altddio_out
Processor
Data
tdint_clk
2
Processor
Scheduler
Status
POS-PHY Level 4 MegaCore Function User Guide
Atlantic
Atlantic
Buffer N
Buffer 0
a0_atxclk
Atlantic
Interface 0
aN_atxclk
(Note 2, 3)
Atlantic
Interface N
txsys_clk
5–11