IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 77

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Description—Transmitter
Block Description
December 2010 Altera Corporation
Parallel to Serial Converter (tx_data_phy_altlvds)
The training sequence includes one IDLE control word, plus ALPHA × 20 words. The
twenty words are separated into ten consecutive tdat words of 16’h0FFF with tctl of
1’b1, followed by ten consecutive tdat words of 16’hF000 with tctl of 1’b0. MaxT is
defined in terms of bytes. In other words, a MaxT=16 value covers one SPI-4.2 cycle.
The range for MaxT is from 0 to 65,535. If MaxT=0, the training pattern is sent only
when in LOSS state (when stat_ts_sync is deasserted) and is not sent periodically.
Training patterns always begin on the rising edge of the clock (tdclk).
If you change the ALPHA and MaxT values at run-time, the values update internally
after the upcoming training pattern is sent. The only exception is when you change
from MaxT=0 to MaxT!= 0. In this case, a training pattern with the new ALPHA and
MaxT values is immediately sent out. Thus, you should change the ALPHA value before
the MaxT value if both values are to be altered during run time.
For control word insertion, two modes are possible: full transmitter or lite transmitter.
The lite transmitter mode is chosen by turning on Lite Transmitter in IP Toolbench.
The lite transmitter uses a smaller, less efficient version of the Atlantic converter that
allows packets to be padded with IDLE characters to a multiple of 16 bytes for 128-bit
variations, or of 8 bytes for 64-bit variations. Although turning on Lite Transmitter
lowers the effective bandwidth rate on the SPI-4.2 data bus, it greatly reduces the logic
consumption.
In IP Toolbench turn off Lite Transmitter for the full transmitter mode. The full
transmitter packs packets more tightly, padding with IDLE characters to multiples of 4
bytes. Thus SOP, COP, and EOP may be combined into a single control word, or may
be in adjacent control words. Turning off Lite Transmitter increases the effective
bandwidth rate on the SPI-4.2 data bus, but also increases the logic consumption.
IDLE control words may be inserted for the following conditions:
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The parallel to serial converter converts the parallel bus and control signals inside the
FPGA into the high-speed SPI-4.2 clock, data, and control signals operating at twice,
four times, or eight times the internal frequency.
Data words are sent on the tdat data bus with the rising and falling edges of tdclk.
Payload data words contain two bytes: bits [15:8] form the first byte, and bits [7:0]
form the second byte. Bit 15 is the most significant bit (MSB), and bit 8 is the least
significant bit (LSB) of the first byte. Bit 7 is the MSB, and bit 0 is the LSB of the second
byte.
For 128- and 64-bit variations, an ALTLVDS megafunction serializes the words into
input high-speed tdat, tctl, and tdclk signals.
The tdclk pin uses an output data pin, using the SERDES to send a repeating binary
10 pattern, guaranteeing minimal skew between the clock and data.
One or two IDLEs occur before a training pattern is inserted
To meet the SOP8 rule
The buffer runs empty or near empty in the shared buffer with embedded address
mode
If no buffer or only one buffer has enough data to start a burst in the individual
buffers mode
POS-PHY Level 4 MegaCore Function User Guide
5–5