IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 32

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–4
DDR and DDR2 SDRAM High-Performance Controller User Guide
Initialization State Machine
The initialization state machine issues the appropriate sequence of command to
initialize the memory devices. It is specific to DDR and DDR2 as each memory type
requires a different sequence of initialization commands.
If you select the AFI mode, then the ALTMEMPHY megafunction is responsible for
initializing the memory. If you select the non-AFI mode, then the controller is
responsible for initializing the memory.
Address and Command Decode
When the state machine wants to issue a command to the memory, it asserts a set of
internal signals. The address and command decode logic turns these into the DDR-
specific RAS/CAS/WE commands.
PHY Interface Logic
When the main state machine issues a write command to the memory, the write data
for that write burst has to be fetched from the write data FIFO. The relationship
between write command and write data depends on the memory type, ALTMEMPHY
megafunction interface type, CAS latency, and the full-rate or half-rate setting. The
PHY interface logic adjusts the timing of the write data FIFO read request signal so
that the data arrives on the external memory interface DQ pins at the correct time.
ODT Generation Logic
The ODT generation logic (not shown) calculates when and for how long to enable the
ODT outputs. It also decides which ODT bit to enable, based on the number of chip
selects in the system.
■
■
Low Power Mode Logic
The low power mode logic (not shown) monitors the local_powerdn_req and
local_self_rfsh_req request signals. This logic also informs the user of the
current low power state via the local_powerdn_ack and local_self_rfsh_ack
acknowledge signals.
If a write/read is happening to:
1 DIMM (1 or 2 Chip Selects)
In the case of a single DIMM, the ODT signal is only asserted during writes. The
ODT signal on the DIMM at mem_cs[0] is always used, even if the write
command on the bus is to mem_cs[1]. In other words, mem_odt[0] is always
asserted even if there are two ODT signals.
2 or more DIMMs
In the multiple DIMM case, the appropriate ODT bit is asserted for both read and
writes. The ODT signal on the adjacent DIMM is enabled as shown.
mem_cs[2] or cs[3]
mem_cs[4] or cs[5]
mem_cs[6] or cs[7]
mem_cs[0]or cs[1]
ODT enabled:
Chapter 4: Functional Description
© March 2009 Altera Corporation
mem_odt[2]
mem_odt[0]
mem_odt[6]
mem_odt[4]
Block Description