IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 77
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IPR-SDRAM/HPDDR
Manufacturer Part Number
IPR-SDRAM/HPDDR
Description
IP CORE Renewal Of IP-SDRAM/HPDDR
Manufacturer
Altera
Datasheet
1.IP-SDRAMHPDDR.pdf
(88 pages)
Specifications of IPR-SDRAM/HPDDR
Software Application
IP CORE, Memory Controllers, SDRAM
Supported Families
Stratix FPGAs, Quartus II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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Chapter 5: Example Design Walkthrough
The Testbench Stages
© March 2009 Altera Corporation
6. Issue an LMR command to ELMR register to enable the memory DLL and set
7. Issue an LMR command to MR register to reset DLL and set operating parameters.
8. Issue a PCH.
9. Issue an ARF.
10. Issue another ARF.
11. Issue an LMR command to MR register to set operating parameters.
12. Issue an LMR command to ELMR register to set default OCD and parameters. 200
In
following the NOP of 200 µs. Steps
is complete by the second yellow cursor. Additional signals are added to simplify
debugging.
Figure
Drive strength, AL, RTT, DQS#, RDQS, OE.
clock cycles after DLL reset, the memory is initialized.
5–2, the expected waveform view of the initialization phase is directly
2
to
9
DDR and DDR2 SDRAM High-Performance Controller User Guide
are expanded to increase detail. Initialization
5–5
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