IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 7
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
IPR-SDRAM/HPDDR
Manufacturer Part Number
IPR-SDRAM/HPDDR
Description
IP CORE Renewal Of IP-SDRAM/HPDDR
Manufacturer
Altera
Datasheet
1.IP-SDRAMHPDDR.pdf
(88 pages)
Specifications of IPR-SDRAM/HPDDR
Software Application
IP CORE, Memory Controllers, SDRAM
Supported Families
Stratix FPGAs, Quartus II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
- Current page: 7 of 88
- Download datasheet (4Mb)
Chapter 1: About These MegaCore Functions
MegaCore Verification
Figure 1–1. System-Level Diagram
Note for
(1) When you choose Instantiate DLL Externally, DLL is instantiated outside the controller.
MegaCore Verification
© March 2009 Altera Corporation
Figure
Pass or Fail
1–1:
Figure 1–1 on page 1–3
that the DDR or DDR2 SDRAM High-Performance Controller MegaCore functions
create for you.
The MegaWizard Plug-In Manager generates an example design, consisting of an
example driver, and your DDR or DDR2 SDRAM high-performance controller
custom variation. The controller instantiates an instance of the ALTMEMPHY
megafunction which in turn instantiates a PLL and DLL. You can optionally
instantiate the DLL outside the ALTMEMPHY megafunction to share the DLL
between multiple instances of the ALTMEMPHY megafunction.
The example design is a fully-functional design that you can simulate, synthesize, and
use in hardware. The example driver is a self-test module that issues read and write
commands to the controller and checks the read data to produce the pass/fail and test
complete signals.
MegaCore verification involves simulation testing. Altera has carried out extensive
random, directed tests with functional test coverage using industry-standard Denali
models to ensure the functionality of the DDR and DDR2 SDRAM high-performance
controller. In addition, Altera performs a wide variety of gate-level tests of the DDR
and DDR2 SDRAM high-performance controllers to verify the post-compilation
functionality of the controllers.
Example Design
Example Driver
Interface
Local
shows a system-level diagram including the example design
DDR/DDR2 SDRAM
PLL
High-Performance
ALTMEMPHY
Megafunction
(Encrypted)
Controller
Control
Logic
DDR and DDR2 SDRAM High-Performance Controller User Guide
DLL
(1)
SDRAM Interface
DDR/DDR2
DDR/DDR2
SDRAM
1–3
Related parts for IPR-SDRAM/HPDDR
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![IPR-SDRAM/DDR](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
IP CORE Renewal Of IP-SDRAM/DDR
Manufacturer:
Altera
Datasheet:
![IPR-SDRAM/DDR2](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
IP CORE Renewal Of IP-SDRAM/DDR2
Manufacturer:
Altera
Datasheet:
![IPR-SDRAM/HPDDR2](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
IP CORE Renewal Of IP-SDRAM/HDDR2
Manufacturer:
Altera
Datasheet:
![IPR-RLDRAMII](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
IP CORE Renewal Of IP-RLDRAMII
Manufacturer:
Altera
Datasheet:
![IPR-HPMCII](/photos/24/19/241941/4696148_tmb.jpg)
Part Number:
Description:
IP CORE Renewal Of IP-HPMCII
Manufacturer:
Altera
Datasheet:
![IPR-RLDII/UNI](/photos/24/19/241946/4696147_tmb.jpg)
Part Number:
Description:
IP CORE Renewal Of IP-RLDII/UNI
Manufacturer:
Altera
Datasheet:
![IPR-SRAM/QDRII](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
IP CORE Renewal Of IP-SRAM/QDRII
Manufacturer:
Altera
Datasheet:
![DK-CYCII-2C20N](/photos/9/20/92074/mfgdk-cycii-2c20nboard_tmb.jpg)
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610IPC-25](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-30](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet: