IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 64

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–36
Figure 4–14. Power-Down Mode
Notes to
(1) The user synchronously asserts the request signal to indicate that the controller should put the memory into the power-down state as soon as
(2) Once the controller is able to issue the correct commands to put the memory into the power-down state, it responds by asserting the acknowledge
(3) If you direct the controller to hold the memory in power-down mode for longer than a refresh cycle, the controller wakes the memory briefly to
(4) The controller holds the memory in power-down mode until you deassert the request signal.
(5) The controller deasserts the acknowledge signal once it has released the memory from the power-down state and once the required timing
Figure 4–15. Self-Refresh Mode
Notes to
(1) You synchronously assert the request signal to indicate that the controller should put the memory into the self-refresh state as soon as possible.
(2) Once the controller is able to issue the correct commands to put the memory into the self-refresh state, it responds by asserting the acknowledge
(3) The controller holds the memory in self-refresh mode until you deassert the request signal.
(4) The controller deasserts the acknowledge signal once it has released the memory from the self-refresh state and once the required timing
DDR and DDR2 SDRAM High-Performance Controller User Guide
possible.
signal.
issue a refresh command at the required time. The local_refresh_ack signal indicates that this has happened - it is asserted for one clock
cycle at approximately the same time as the refresh command is issued. If Enable user auto-refresh controls is turned on, you must issue refresh
requests via the local_refresh_req input at the appropriate time, even if you have also requested power-down mode.
parameters are met.
signal.
parameters are met.
Figure
Figure
4–14:
4–15:
clk
local_powerdn_req
local_powerdn_ack
local_refresh_ack
clk
local_self_rfsh_req
local_self_rfsh_ack
Auto-Precharge Commands
The auto-precharge read and auto-precharge write commands allow you to indicate
to the memory device that this read or write command is the last access to the
currently open row. The memory device automatically closes (auto-precharges) the
page it is currently accessing so that the next access to the same bank is quicker. This
command is particularly useful for applications that require fast random accesses.
Request an auto-precharge by asserting the local_autopch input at the same time
you assert the local_read_req or local_write_req signal. The timing and rules
of the local_autopch input follow the basic Avalon-MM interface specifications
(refer to
asserted it, the signal must stay asserted until the local_ready signal is high, which
indicates that the current request has been accepted.
Avalon Interface
(1)
(1)
(2)
(2)
Specifications). You can assert it anytime, but once you have
(3)
(4)
(3)
Chapter 4: Functional Description
© March 2009 Altera Corporation
(5)
(4)
Interfaces and Signals