IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 67

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Interfaces and Signals
Table 4–7. Local Interface Signals (Part 1 of 4)
© March 2009 Altera Corporation
local_address[]
Signal Name
Table 4–7 on page 4–39
controller local interface signals.
Direction
Input
Memory address at which the burst should start.
■
The width of this bus is sized using the following equation:
For one chip select:
width = bank bits + row bits + column bits – 1
For multiple chip selects:
width = chip bits + bank bits + row bits + column bits – 1
If the bank address is 2 bits wide, row is 13 bits wide and column is 10 bits
wide, then the local address is 24 bits wide. To map local_address to
bank, row and column address:
local_address[23:22] = bank address [1:0]
local_address[21:9] = row address [13:0]
local_address [8:0] = col_address[9:1]
The least significant bit (LSB) of the column address (multiples of four) on the
memory side is ignored, because the local data width is twice that of the
memory data bus width.
■
The width of this bus is sized using the following equation:
For one chip select:
width = bank bits + row bits + column bits – 2
For multiple chip selects:
width = chip bits + bank bits + row bits + column bits – 2
If the bank address is 2 bits wide, row is 13 bits wide and column is 10 bits
wide, then the local address is 23 bits wide. To map local_address to
bank, row and column address:
local_address is 23 bits wide
local_address[22:21] = bank address
local_address[20:8] = row address [13:0]
local_address [7:0] = col_address[9:2]
Two LSBs of the column address on the memory side are ignored, because the
local data width is four times that of the memory data bus width.
1
Full rate controllers
Half rate controllers
shows the DDR and DDR2 SDRAM high-performance
<variation_name>_example_top.v or vhd file
You can get the information on address mapping from the
DDR and DDR2 SDRAM High-Performance Controller User Guide
Description
.
4–39