IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 79

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Example Design Walkthrough
The Testbench Stages
Functional Memory Use
© March 2009 Altera Corporation
f
1
Once training and calibration are complete, the ALTMEMPHY sequencer asserts
seq_cal_complete (AFI mode) or ctrl_usr_mode_rdy (non-AFI mode) to the
memory controller, which is then copied to the local interface as the signal
local_init_done. Local interface read and write transactions can now occur.
In the example testbench, the example driver now performs 16 writes followed by 16
reads to incremental address locations spanning column, row and bank locations
using LFSR pattern based on the address being written.
Adding the following controller signals to your simulation provides you more
information on the example driver operation:
For external memory interface signals, refer to the
Megafunction User Guide
You can use the example driver to test a custom controller and ALTMEMPHY
megafunction combination. The driver performs a series of writes to the external
memory, followed by a series of reads to the same locations, and compares the read
and write data.
This comparison results in dynamic “pass not fail per byte” (pnf_per_byte)
signals, and a latched combined pass not fail (pnf, 1=pass 0=fail) signal. Each
completed series of writes and reads is signaled via the test_complete signal, and
then the test repeats.
The example testbench stops when either test_complete is asserted or when
200,000 mem_clk cycles after the t
clock_source
global_reset_n
test_complete
pnf
pnf_per_byte
mem_local_init_done
mem_local_ready
mem_local_addr
mem_local_col_addr
mem_local_cs_addr
mem_local_read_req
mem_local_rdata
mem_local_rdata_valid
mem_local_write_req
mem_local_wdata
mem_local_be
mem_local_size
mem_local_wdata_req
mem_local_burstbegin
(ALTMEMPHY).
(Native interface only)
(Avalon-MM interface only)
INIT
time.
DDR and DDR2 SDRAM High-Performance Controller User Guide
External Memory PHY Interface
5–7