VS6624Q0KP STMicroelectronics, VS6624Q0KP Datasheet - Page 38
VS6624Q0KP
Manufacturer Part Number
VS6624Q0KP
Description
Display Modules & Development Tools CAMERA MODULE SINGLE CHIP 1.3MEGA
Manufacturer
STMicroelectronics
Datasheet
1.VS6624Q0KP.pdf
(106 pages)
Specifications of VS6624Q0KP
Description/function
Camera Module
Interface Type
Two-Wire Serial
Data Bus Width
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Host communication - I²C control interface
10.3
10.4
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Data valid
The data on SDA is stable during the high period of SCL. The state of SDA is changed
during the low phase of SCL. The only exceptions to this are the start (S) and stop (P)
conditions as defined below. (See
Figure 22. SDA data valid
Start (S) and Stop (P) conditions
A START (S) condition defines the start of a V2W message. It consists of a high to low
transition on SDA while SCL is high.
A STOP (P) condition defines the end of a V2W message. It consists of a low to high
transition on SDA while SCL is high.
After STOP condition the bus is considered free for use by other devices. If a repeated
START (Sr) is used instead of a stop then the bus stays busy. A START (S) and a repeated
START (Sr) are considered to be functionally equivalent.
Figure 23. START and STOP conditions
SDA
SCL
condition
START
S
SDA
SCL
I²C slave interface
Data valid
Data line
stable
Data change
for full timing specification).
Data valid
Data line
stable
VL6624/VS6624
condition
STOP
P
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