TLE8209-2SA Infineon Technologies, TLE8209-2SA Datasheet - Page 24

• Manufacturer Part Number: TLE8209-2SA
• Description: IC H-BRIDGE SPI PROG DSO-20
• Manufacturer: Infineon Technologies

Specifications of TLE8209-2SA

• Applications: DC Motor Driver
• Number Of Outputs: 1
• Voltage - Load: 4.5 V ~ 28 V
• Voltage - Supply: 4.4 V ~ 5.25 V
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (0.433", 11.0mm Width) Exposed Pad
• Packages: PG-DSO-20
• Current Limit (min.): 7.7 A
• Rthjc (max): 1.6 K/W
• Quiescent Current (max.): 20 µA
• Operating Range: 4.5 - 28 V
• Rds (on) (typ./switch): 125.0 mOhm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -

9
The serial SPI interface establishes a communication link between TLE8209-2SA and the systems
microcontroller. The TLE8209-2SA always operates in slave mode whereas the controller provides the master
function. The maximum baud rate is 2 MBaud.
By applying an active slave select signal at SS the TLE8209-2SA is selected by the SPI-master. SI is the data
input (Slave In), SO the data output (Slave Out). Via SCK (Serial Clock Input) the SPI-clock is provided by the
master. In case of inactive slave select signal (High) the data output SO goes into tristate.
The first two bits of an instruction may be used to establish an extended device-addressing. This gives the
opportunity to operate up to 4 Slave-devices sharing one common SS signal from the Master-Unit (see
Figure 14
9.1
1. During active reset conditions the SPI is driven into its default state. The output SO is set to high impedance
2. If the slave select signal at SS is inactive (high), the state machine is forced to wait for the following instruction.
3. During active (low) state of the select signal SS the falling edge of the serial clock signal SCK will be used to
4. In order to establish the option of extended addressing the upper two bits of the instruction byte (i.e. the first
Data Sheet
(tristate). When reset becomes inactive, the state machine enters into a wait state for the next instruction.
latch the input data at SI. Output data at SO are driven with the rising edge of SCK. Further processing of the
data according to the instruction (i.e. modification of internal registers) will be triggered by the rising edge of
the SS signal.
two SI bits of a frame) are reserved to send a chip address. To avoid a bus conflict the output SO will remain
tristate during the addressing phase of a frame (i.e. until the address bits are recognized as a valid chip
SCK
ABE
DIS
SS
SO
SI
SPI Interface
SPI Block Diagram
General SPI Characteristics
shift-register
OR
8
24
DIA_REG
Reset
SPI-Control:
-> state machine
-> clock counter
-> instruction recognition
8
Diagnostics
Rev. 1.0, 2010-02-16
TLE8209-2SA
SPI Interface
Figure
16).