LS-X2280-BASE-PC-N Lattice, LS-X2280-BASE-PC-N Datasheet - Page 11

• Manufacturer Part Number: LS-X2280-BASE-PC-N
• Description: MCU, MPU & DSP Development Tools ispLEVER Base MachXO -2280 Std Dev Kit
• Manufacturer: Lattice

Specifications of LS-X2280-BASE-PC-N

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 6. Oscillator Positions
Note: XU2 pin 9 is routed to one of the two PLLs included on larger MachXO devices. These MachXO PLLs are not
available on the MachXO640 device. XU2 pin 9 provides input to the PLL_T input pin M5.
JP2 and JP3 are routed to the second set of PLL input pins on the MachXO device. On the MachXO640, these
input pins are general purpose I/O. For larger MachXO devices, these same I/O pins are combination general pur-
pose I/O and PLL inputs. The traces from JP2/JP3 are 50 ohm impedance, and have the same resistor pad struc-
ture described in Figure 6. JP2/JP3 provide the ability to insert differential clock sources. Review the schematic for
the exact part reference numbers of the resistors.
The second way to provide a clock to the ispClock5610 is to use JP4 and JP5 SMA connectors. These SMA con-
nectors are not installed by default. Also, by default the positive input from JP4 is disconnected from the
ispClock5610. Beneath the ispClock5610 on the reverse side of the board are two resistor sites: R158 and R159.
R158 connects XU2 pin 10 to the ispClock5610 positive clock input. R159 connects JP4 to the ispClock positive
clock input. By default, R158 has a zero ohm resistor installed and R159 is left empty. This is done to prevent unde-
sirable artifacts from appearing on the input clock due to trace stubs. R158 and R159 are placed in a way to reduce
the length of any stub traces to an absolute minimum. When supplying a clock from JP4/JP5, R158 should be
moved to R159 in order to connect JP4 to the ispClock5610.
Table 9. ispClock5610 Clock Source
Once the clock source to the ispClock device has been defined, the ispClock can be programmed to generate clock
frequencies for the MachXO. The ispClock5610 has five outputs from the internal PLL (0-4). The first four, 0-3, are
applied directly to the MachXO clock input pins. The fifth output is brought out to TP2 and TP3, adjacent to the isp-
Clock chip.
Table 10. Clock Connections
to ispClock
Full-size
JP9
Pin 1
1-2: Oscillator enabled
2-3: Oscillator disabled
ispClock5610 Pin
MachXO PLL
CLK_OUT0
CLK_OUT1
CLK_OUT2
CLK_OUT3
Full-size to
Resistor
R158
R159
11
Positive Source
ispClock5610
XU2 pin 10
JP4
MachXO Pin
to ispClock
Half-size
M9
D7
N9
MachXO Standard Evaluation Board
A9
Revisions 001 & 002 User’s Guide
MachXO PLL
Half-size to